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Xilinx unisim typo

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Henry Styles 2018-01-10 14:23:50 -08:00 committed by Wesley W. Terpstra
parent 33c88b8cc4
commit f9dc552ddc
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/ip/xilinx/Unisim.scala
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@ -33,7 +33,7 @@ extends BlackBox(
"DIFF_TERM" -> booleanToVerilogStringParam(DIFF_TERM),
"DQS_BIAS" -> booleanToVerilogStringParam(DQS_BIAS),
"IBUF_DELAY_VALUE" -> IntParam(IBUF_DELAY_VALUE),
"IBUDF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR),
"IBUF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR),
"IFD_DELAY_VALUE" -> StringParam(IFD_DELAY_VALUE),
"IOSTANDARD" -> StringParam(IOSTANDARD)
)