riscv/fpga-shells
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Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
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Scala 89.5%
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Henry Styles ba7beb676d
Merge pull request #14 from sifive/vc707_mig_pcie_traits 
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits
2017-11-01 16:58:44 -07:00
src/main/scala VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock 2017-11-01 14:23:07 -07:00
xilinx VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock 2017-11-01 14:23:07 -07:00
.gitignore Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00