Megan WachsandGitHub 32d4083890 Merge pull request #6 from sifive/signal_bundles ...

signal_bundles: Use the new way as .fromPorts is gone

2017-09-25 11:20:44 -07:00

src/main/scala

signal_bundles: Use the new way as .fromPorts is gone

2017-09-22 13:31:11 -07:00

xilinx

Use a file instead of environment variable to pass VSRCS into Vivado

2017-09-19 14:12:23 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%