riscv/fpga-shells
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Add clock and proper reset feedback to ml507

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This commit is contained in:
Klemens Schölhorn 2018-04-19 01:29:15 +02:00
parent 5db71d11c2
commit b2b19cc822
1 changed files with 6 additions and 4 deletions
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10
src/main/scala/shell/xilinx/ML507Shell.scala
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@ -57,7 +57,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// active high reset
val reset = IO(Input(Bool()))
val reset_led = IO(Output(Bool()))
// LED
val led = IO(Vec(8, Output(Bool())))
@ -87,6 +86,9 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
val sw_6 = IO(Input(Bool()))
val sw_7 = IO(Input(Bool()))
// Feedback
val clock_led = IO(Output(Clock()))
val reset_led = IO(Output(Bool()))
//-----------------------------------------------------------------------
// Wire declrations
@ -120,9 +122,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// Allow the debug module to reset everything. Resets the MIG
sys_reset := reset | dut_ndreset
// Status LED for reset
reset_led := reset
//-----------------------------------------------------------------------
// Clock Generator
//-----------------------------------------------------------------------
@ -152,6 +151,9 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
safe_reset.io.clock4 := dut_clock
dut_reset := safe_reset.io.reset4
// Setup feedback
clock_led := dut_clock
reset_led := dut_reset
//-----------------------------------------------------------------------
// UART