riscv/fpga-shells
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Remove unused signals (pcie, mem) from ml507 shell

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This commit is contained in:
Klemens Schölhorn 2018-04-19 01:27:35 +02:00
parent 0b421d5645
commit f4ae1d469f
1 changed files with 3 additions and 34 deletions
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37
src/main/scala/shell/xilinx/ML507Shell.scala
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@ -97,7 +97,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
val dut_clock = Wire(Clock())
val dut_reset = Wire(Bool())
val dut_resetn = Wire(Bool())
val dut_ndreset = Wire(Bool())
@ -108,20 +107,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
val do_reset = Wire(Bool())
val mig_mmcm_locked = Wire(Bool())
val mig_sys_reset = Wire(Bool())
val mig_clock = Wire(Clock())
val mig_reset = Wire(Bool())
val mig_resetn = Wire(Bool())
val pcie_dat_reset = Wire(Bool())
val pcie_dat_resetn = Wire(Bool())
val pcie_cfg_reset = Wire(Bool())
val pcie_cfg_resetn = Wire(Bool())
val pcie_dat_clock = Wire(Clock())
val pcie_cfg_clock = Wire(Clock())
val mmcm_lock_pcie = Wire(Bool())
val clk_locked = Wire(Bool())
@ -156,33 +141,17 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
//-----------------------------------------------------------------------
do_reset := !clk_locked || sys_reset
mig_resetn := !mig_reset
dut_resetn := !dut_reset
pcie_dat_resetn := !pcie_dat_reset
pcie_cfg_resetn := !pcie_cfg_reset
// TODO: adapt for ml507?
val safe_reset = Module(new vc707reset)
safe_reset.io.areset := do_reset
safe_reset.io.clock1 := mig_clock
mig_reset := safe_reset.io.reset1
safe_reset.io.clock2 := pcie_dat_clock
pcie_dat_reset := safe_reset.io.reset2
safe_reset.io.clock3 := pcie_cfg_clock
pcie_cfg_reset := safe_reset.io.reset3
safe_reset.io.clock1 := dut_clock
safe_reset.io.clock2 := dut_clock
safe_reset.io.clock3 := dut_clock
safe_reset.io.clock4 := dut_clock
dut_reset := safe_reset.io.reset4
//overrided in connectMIG and connect PCIe
//provide defaults to allow above reset sequencing logic to work without both
mig_clock := dut_clock
pcie_dat_clock := dut_clock
pcie_cfg_clock := dut_clock
mig_mmcm_locked := UInt("b1")
mmcm_lock_pcie := UInt("b1")
//-----------------------------------------------------------------------
// UART