Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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385ffa7d9a
@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
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# Platform specific constraints
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set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
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set_property IOB TRUE [get_cells "uart_rx_sync_0"]
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set_property IOB TRUE [get_cells "uart_rx_sync_0_reg"]
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# PCI Express
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#FMC 1 refclk
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@ -40,11 +40,11 @@ set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
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create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
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set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
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set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
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set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
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set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp}]
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set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn}]
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set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
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set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
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set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp}]
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set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn}]
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# JTAG
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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