Henry StylesandGitHub eaf1c3ed54 Merge pull request #11 from sifive/vc707_use_ip_io_bundles ...

VC707 use IP IO bundles

2017-10-24 17:49:31 -07:00

src/main/scala

VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals

2017-10-23 16:53:59 -07:00

xilinx

VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP

2017-10-23 17:27:36 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%