Henry Styles b7ee0ab0f0 fix PCIe vc707 design contraints : PCIe pins and UART RX sync register

2017-09-07 10:41:12 -07:00

src/main/scala

Fix the package path for xilinx vc707mig

2017-08-18 14:47:03 -07:00

xilinx

fix PCIe vc707 design contraints : PCIe pins and UART RX sync register

2017-09-07 10:41:12 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

build.sbt

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%