Logo
Explore Help
Sign In
riscv/fpga-shells
Watch 1
Star 0 Fork 0
Code Releases Activity
51 Commits 2 Branches 0 Tags
8329b232e23c63267c0ea9f996199af38afc52f5
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
klemens 8329b232e2 Hold ml507 in reset while clock not locked
2018-04-19 01:25:31 +02:00
src/main/scala
Hold ml507 in reset while clock not locked
2018-04-19 01:25:31 +02:00
xilinx
prologue: support the absence of an xdc/tcl constraint file
2018-02-25 15:21:03 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
S
Description
Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
682 KiB
0 Stars 1 Watchers 0 Forks
Languages
Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%
Powered by Gitea Version: 28.2.0 Page: 701ms Template: 195ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API