Henry StylesandWesley W. Terpstra f9dc552ddc Xilinx unisim typo

2018-02-08 07:21:44 -08:00

src/main/scala

Xilinx unisim typo

2018-02-08 07:21:44 -08:00

xilinx

VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock

2017-11-01 14:23:07 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%