riscv/fpga-shells
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  • b49f5cfa78 Reduce crossing and queue depths to save space and ease timing ml507 Klemens Schölhorn 2018-05-14 20:07:01 +0200
  • 700e6b640d Document address extraction for the mig Klemens Schölhorn 2018-05-13 19:52:38 +0200
  • 12cb1c2fa5 Implement XilinxML507MIGToTL TL to MIG converter Klemens Schölhorn 2018-05-10 21:40:52 +0200
  • 7e53be49f9 Fix memory controller signal name Klemens Schölhorn 2018-05-10 02:27:31 +0200
  • 77694a6741 Add clock generation for the mig Klemens Schölhorn 2018-05-10 01:04:52 +0200
  • 589e9960c0 Move XilinxML507MIGToTL and MIG into a separate clock domain Klemens Schölhorn 2018-05-10 00:30:23 +0200
  • 2707fa59a4 Add XilinxML507MIG periphery and connect top level signals Klemens Schölhorn 2018-05-10 00:29:22 +0200
  • 3797385a8c Import ml507 mig TL implementation stub Klemens Schölhorn 2018-05-09 23:17:08 +0200
  • 79b53cf2ae Add dip switches and clean up top interface Klemens Schölhorn 2018-05-01 00:07:58 +0200
  • 5bcc4e82fd Generate separate processor and terminal clocks Klemens Schölhorn 2018-04-30 22:52:02 +0200
  • 9c06418352 Add terminal/dvi io (unsing the same clock for now) Klemens Schölhorn 2018-04-30 00:41:05 +0200
  • b2b19cc822 Add clock and proper reset feedback to ml507 Klemens Schölhorn 2018-04-19 01:29:15 +0200
  • 5db71d11c2 Fix polarity of buttons and dips on the ml507 Klemens Schölhorn 2018-04-19 01:28:36 +0200
  • f4ae1d469f Remove unused signals (pcie, mem) from ml507 shell Klemens Schölhorn 2018-04-19 01:27:35 +0200
  • 0b421d5645 Remove incorrect jtag pin constraints form ml507 Klemens Schölhorn 2018-04-19 01:26:15 +0200
  • 8329b232e2 Hold ml507 in reset while clock not locked Klemens Schölhorn 2018-04-19 01:25:31 +0200
  • 2ff28e6af6 Add status indication led for the reset button Klemens Schölhorn 2018-04-18 00:26:43 +0200
  • 41362a1cb5 Remove unused UART signals (rs and cs) from ml507 Klemens Schölhorn 2018-04-18 00:26:00 +0200
  • e9625bf8ee Add initial ML507Shell stub based on VC707Shell Klemens Schölhorn 2018-04-12 00:42:46 +0200
  • 9d02f530fc vc707shell: work-around too many '++'s => stack overflow issue master Wesley W. Terpstra 2018-03-22 18:08:32 -0700
  • 080119ec7a
         chiplink: add pinout (#20) Wesley W. Terpstra 2018-03-22 17:13:25 -0700
  • 0ca9f2bb66
         periphery: bus api update (#17) Henry Cook 2018-03-01 01:16:04 -0800
  • 1dda525578 prologue: support the absence of an xdc/tcl constraint file Wesley W. Terpstra 2018-02-25 15:21:03 -0800
  • 6df6db25de
         Merge pull request #18 from sifive/dynamic-clock-groups Wesley W. Terpstra 2018-02-25 15:08:15 -0800
  • 4386187016 vc707: add clock groups dynamically iff they exist Wesley W. Terpstra 2018-02-25 14:33:32 -0800
  • b7afc83a34 xilinx prologue: support tcl for constraints Wesley W. Terpstra 2018-02-25 14:32:39 -0800
  • 17e13a3a50
         Merge pull request #16 from sifive/chiplink-100 Wesley W. Terpstra 2018-02-08 15:40:16 -0800
  • 8519ba8d4e vc707: setup 100MHz PLL Wesley W. Terpstra 2018-01-24 17:27:29 -0800
  • 506d2da883 vc707: update constraints to match correct mmcm Wesley W. Terpstra 2018-01-23 14:28:56 -0800
  • 9c38f20333 vc707 axi: move addresses to line up with ChipLink Wesley W. Terpstra 2018-01-23 14:28:22 -0800
  • 61ece0bf00 VC707 Shell : additional skewed clocks Henry Styles 2018-01-19 12:08:41 -0800
  • 0fdbb778bf VC707 Shell : move DebugJTAG pins and connect function into a separate mix-in Henry Styles 2018-01-17 16:03:52 -0800
  • 045b290fbd VC707 JTAG support throught XM105 FMC or reuse of LCD header Henry Styles 2018-01-10 15:23:17 -0800
  • f9dc552ddc Xilinx unisim typo Henry Styles 2018-01-10 14:23:50 -0800
  • 33c88b8cc4 Move Xilinx unisims into separate file Henry Styles 2017-12-22 16:44:08 -0800
  • 8b0d7ec91a
         TransferSizes: just because a device CAN do more does not mean it should (#15) Wesley W. Terpstra 2017-12-10 00:42:11 -0800
  • ba7beb676d
         Merge pull request #14 from sifive/vc707_mig_pcie_traits Henry Styles 2017-11-01 16:58:44 -0700
  • e1bfb75188 VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock Henry Styles 2017-10-31 16:03:24 -0700
  • df8e6b8e8c
         xilinxvc707pciex1: use new node-style API and abstract crossing (#13) Wesley W. Terpstra 2017-10-28 12:27:24 -0700
  • 65ac5d4588 xilinxVC707mig: convert to the island pattern (#12) Wesley W. Terpstra 2017-10-26 16:38:52 -0700
  • eaf1c3ed54 Merge pull request #11 from sifive/vc707_use_ip_io_bundles Henry Styles 2017-10-24 17:49:31 -0700
  • dc6bb40d1b VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP Henry Styles 2017-10-23 17:27:36 -0700
  • 61b167e8d9 VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals Henry Styles 2017-10-23 16:53:59 -0700
  • d8e50c7646 TLToAXI4: remove now unnecessary argument (#10) Wesley W. Terpstra 2017-10-12 14:37:21 -0700
  • 66e5ac2e9e Merge pull request #8 from sifive/replace-env-vars-with-cli-args Richard Xia 2017-10-04 14:28:10 -0700
  • 9593e5eee6 Restructure Tcl script entrypoint. Richard Xia 2017-10-03 18:24:18 -0700
  • 4af0552374 diplomacy: update to new API (#7) Wesley W. Terpstra 2017-09-27 16:32:43 -0700
  • 32d4083890 Merge pull request #6 from sifive/signal_bundles Megan Wachs 2017-09-25 11:20:44 -0700
  • bf48e2c7c4 signal_bundles: Use the new way as .fromPorts is gone Megan Wachs 2017-09-22 13:31:11 -0700
  • e9019d7570 Merge pull request #5 from sifive/vivado_vsrcs_using_file Henry Styles 2017-09-19 14:13:36 -0700
  • 97e628639a Use a file instead of environment variable to pass VSRCS into Vivado Henry Styles 2017-09-19 14:12:23 -0700
  • 2bed0c30dc correct invoke of board specific ip.tcl Henry Styles 2017-09-08 23:20:55 -0700
  • 07b2ae07d2 Merge pull request #4 from sifive/vc707_2GB Henry Styles 2017-09-08 16:09:18 -0700
  • 9f75e6eb59 Support both 4G and 1GB DIMM configuration for VC707 Henry Styles 2017-08-21 17:30:01 -0700
  • e49f49686d Merge pull request #1 from sifive/synchronizers Megan Wachs 2017-09-07 13:33:26 -0700
  • 31650a2d23 Merge remote-tracking branch 'origin/master' into synchronizers Megan Wachs 2017-09-07 10:46:03 -0700
  • 385ffa7d9a Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc Henry Styles 2017-09-07 10:42:32 -0700
  • b7ee0ab0f0 fix PCIe vc707 design contraints : PCIe pins and UART RX sync register Henry Styles 2017-09-07 10:41:12 -0700
  • cab572fab2 synchronizers: decided that ShiftRegInit should be reversed as the others. Megan Wachs 2017-09-07 09:54:35 -0700
  • fd70d118d3 synchronizers: Update constraints to match new hierarchy for synchronizers Megan Wachs 2017-09-07 07:46:21 -0700
  • 13671f906d synchronizers: Use new primitives Megan Wachs 2017-09-06 11:00:25 -0700
  • 2389e6e957 Fix the package path for xilinx vc707mig Shreesha Srinath 2017-08-18 14:47:03 -0700
  • 38afe2957f Fixing typos in the tcl script Shreesha Srinath 2017-08-18 11:34:35 -0700
  • ae767458af Pass debug hooks through project-specific makefiles Shreesha Srinath 2017-08-18 11:27:02 -0700
  • c58e79f155 vc707: Updates to the constraints and shell Shreesha Srinath 2017-08-17 18:51:01 -0700
  • ab8cf0775f Initial commit for fpga-shells Shreesha Srinath 2017-08-16 11:23:45 -0700