Merge pull request #1 from sifive/synchronizers
synchronizers: Use new primitives
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commit
e49f49686d
@ -7,11 +7,11 @@ import chisel3.experimental.{RawModule, Analog, withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.util.{ShiftRegister}
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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@ -201,11 +201,8 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
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val uartParams = p(PeripheryUARTKey)
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if (!uartParams.isEmpty) {
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// synchronize uart_rx
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val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx"))
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// uart connections
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dut.uart(0).rxd := uart_rx_sync
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dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync"))
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uart_tx := dut.uart(0).txd
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}
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}
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@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
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# Platform specific constraints
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set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
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set_property IOB TRUE [get_cells "uart_rx_sync_0_reg"]
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set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"]
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# PCI Express
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#FMC 1 refclk
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