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Henry Styles 385ffa7d9a Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:42:32 -07:00
2017-08-16 11:23:45 -07:00
2017-08-16 11:23:45 -07:00
Description
Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
682 KiB
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Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%