This website requires JavaScript.
Explore
Help
Sign In
riscv
/
fpga-shells
Watch
1
Star
0
Fork
0
You've already forked fpga-shells
Code
Releases
Activity
41
Commits
2
Branches
0
Tags
b7afc83a34c54af35b817be2709ed0215b5c1b43
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Wesley W. Terpstra
b7afc83a34
xilinx prologue: support tcl for constraints
2018-02-25 14:32:39 -08:00
src/main
/scala
vc707: setup 100MHz PLL
2018-02-08 07:21:45 -08:00
xilinx
xilinx prologue: support tcl for constraints
2018-02-25 14:32:39 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
Description
Freedom FPGA mappings (
https://github.com/sifive/fpga-shells
)
682
KiB
Languages
Scala
89.5%
Tcl
7.8%
Verilog
2%
Makefile
0.7%