Henry StylesandGitHub e9019d7570 Merge pull request #5 from sifive/vivado_vsrcs_using_file ...

Use a file instead of environment variable to pass VSRCS into Vivado

2017-09-19 14:13:36 -07:00

src/main/scala

Support both 4G and 1GB DIMM configuration for VC707

2017-09-08 15:52:53 -07:00

xilinx

Use a file instead of environment variable to pass VSRCS into Vivado

2017-09-19 14:12:23 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%