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riscv
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fpga-shells
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Freedom FPGA mappings (
https://github.com/sifive/fpga-shells
)
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682
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Scala
89.5%
Tcl
7.8%
Verilog
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79b53cf2ae
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Klemens Schölhorn
79b53cf2ae
Add dip switches and clean up top interface
2018-05-01 00:07:58 +02:00
src/main
/scala
Add dip switches and clean up top interface
2018-05-01 00:07:58 +02:00
xilinx
prologue: support the absence of an xdc/tcl constraint file
2018-02-25 15:21:03 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00