riscv/fpga-shells
1
0
Fork 0
Code Releases Activity

Merge pull request #16 from sifive/chiplink-100

Browse Source 
Chiplink 100
This commit is contained in:
Wesley W. Terpstra 2018-02-08 15:40:16 -08:00 committed by GitHub
commit 17e13a3a50
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 506 additions and 141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

320
src/main/scala/ip/xilinx/Unisim.scala Normal file
View File

@ -0,0 +1,320 @@
// See LICENSE for license details.
package sifive.fpgashells.ip.xilinx
import Chisel._
import chisel3.{Input, Output}
import chisel3.experimental.{Analog, attach, StringParam, RawParam, IntParam, DoubleParam}
import sifive.blocks.devices.pinctrl.{BasePin}
object booleanToVerilogVectorParam extends (Boolean => RawParam) {
def apply(b : Boolean) : RawParam = if(b) RawParam("1") else RawParam("0")
}
object booleanToVerilogStringParam extends (Boolean => StringParam) {
def apply(b : Boolean) : StringParam = if(b) StringParam("""TRUE""") else StringParam("""FALSE""")
}
/** IBUFDS -- SelectIO Differential Input */
class IBUFDS(
CAPACITANCE : String = "DONT_CARE",
DIFF_TERM : Boolean = false,
DQS_BIAS : Boolean = false,
IBUF_DELAY_VALUE : Int = 0,
IBUF_LOW_PWR : Boolean = true,
IFD_DELAY_VALUE : String = "AUTO",
IOSTANDARD : String = "DEFAULT"
)
extends BlackBox(
Map(
"CAPACITANCE" -> StringParam(CAPACITANCE),
"DIFF_TERM" -> booleanToVerilogStringParam(DIFF_TERM),
"DQS_BIAS" -> booleanToVerilogStringParam(DQS_BIAS),
"IBUF_DELAY_VALUE" -> IntParam(IBUF_DELAY_VALUE),
"IBUF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR),
"IFD_DELAY_VALUE" -> StringParam(IFD_DELAY_VALUE),
"IOSTANDARD" -> StringParam(IOSTANDARD)
)
) {
val io = IO(new Bundle {
val O = Bool(OUTPUT)
val I = Bool(INPUT)
val IB = Bool(INPUT)
})
}
/** IBUFG -- Clock Input Buffer */
class IBUFG extends BlackBox {
val io = IO(new Bundle {
val O = Output(Clock())
val I = Input(Clock())
})
}
object IBUFG {
def apply (pin: Clock): Clock = {
val pad = Module (new IBUFG())
pad.io.I := pin
pad.io.O
}
}
/** IBUFDS_GTE2 -- Differential Signaling Input Buffer */
class IBUFDS_GTE2(
CLKCM_CFG : Boolean = true,
CLKRCV_TRST : Boolean = true,
CLKSWING_CFG : Int = 3
)
extends BlackBox(
Map(
"CLKCM_CFG" -> booleanToVerilogStringParam(CLKCM_CFG),
"CLKRCV_TRST" -> booleanToVerilogStringParam(CLKCM_CFG),
"CLKSWING_CFG" -> IntParam(CLKSWING_CFG)
)
) {
val io = IO(new Bundle {
val O = Bool(OUTPUT)
val ODIV2 = Bool(OUTPUT)
val CEB = Bool(INPUT)
val I = Bool(INPUT)
val IB = Bool(INPUT)
})
}
/** IDDR - 7 Series SelectIO DDR flop */
class IDDR(
DDR_CLK_EDGE : String = "OPPOSITE_EDGE",
INIT_Q1 : Boolean = false,
INIT_Q2 : Boolean = false,
IS_C_INVERTED : Boolean = false,
IS_D_INVERTED : Boolean = false,
SRTYPE : String = "SYNC"
)
extends BlackBox(
Map(
"DDR_CLK_EDGE" -> StringParam(DDR_CLK_EDGE),
"INIT_Q1" -> booleanToVerilogVectorParam(INIT_Q1),
"INIT_Q2" -> booleanToVerilogVectorParam(INIT_Q2),
"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
"IS_D_INVERTED" -> booleanToVerilogVectorParam(IS_D_INVERTED),
"SRTYPE" -> StringParam(SRTYPE)
)
) {
val io = IO(new Bundle {
val Q1 = Output(Bool())
val Q2 = Output(Bool())
val C = Input(Bool())
val CE = Input(Bool())
val D = Input(Bool())
val R = Input(Bool())
val S = Input(Bool())
})
}
/** IDELAYCTRL - 7 Series SelectIO */
class IDELAYCTRL(
sim_device : String = "7SERIES"
)
extends BlackBox(
Map(
"SIM_DEVICE" -> StringParam(sim_device)
)
) {
val io = IO(new Bundle {
val RDY = Output(Bool())
val REFCLK = Input(Bool())
val RST = Input(Bool())
})
}
/** IDELAYE2 -- 7 Series SelectIO ILogic programmable delay. */
class IDELAYE2(
CINVCTRL_SEL : Boolean = false,
DELAY_SRC : String = "IDATAIN",
HIGH_PERFORMANCE_MODE : Boolean = false,
IDELAY_TYPE : String = "FIXED",
IDELAY_VALUE : Int = 0,
IS_C_INVERTED : Boolean = false,
IS_DATAIN_INVERTED : Boolean = false,
IS_IDATAIN_INVERTED : Boolean = false,
PIPE_SEL : Boolean = false,
REFCLK_FREQUENCY : Double = 200.0,
SIGNAL_PATTERN : String = "DATA",
SIM_DELAY_D : Int = 0
)
extends BlackBox(
Map(
"CINVCTRL_SEL" -> booleanToVerilogStringParam(CINVCTRL_SEL),
"DELAY_SRC" -> StringParam(DELAY_SRC),
"HIGH_PERFORMANCE_MODE" -> booleanToVerilogStringParam(HIGH_PERFORMANCE_MODE),
"IDELAY_TYPE" -> StringParam(IDELAY_TYPE),
"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
"IS_DATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_DATAIN_INVERTED),
"IS_IDATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_IDATAIN_INVERTED),
"PIPE_SEL" -> booleanToVerilogStringParam(PIPE_SEL),
"REFCLK_FREQUENCY" -> DoubleParam(REFCLK_FREQUENCY),
"SIGNAL_PATTERN" -> StringParam(SIGNAL_PATTERN),
"SIM_DELAY_D" -> IntParam(SIM_DELAY_D)
)
) {
val io = IO(new Bundle {
val DATAOUT = Output(Bool())
val CNTVALUEOUT = Output(UInt(5.W))
val C = Input(Bool())
val CE = Input(Bool())
val CINVCTRL = Input(Bool())
val DATAIN = Input(Bool())
val IDATAIN = Input(Bool())
val INC = Input(Bool())
val LD = Input(Bool())
val LDPIPEEN = Input(Bool())
val REGRST = Input(Bool())
val CNTVALUEIN = Input(UInt(5.W))
})
}
/** IOBUF -- Bidirectional IO Buffer. */
//Cannot convert to BlackBox because of line
//val IO = IO(Analog(1.W))
//is illegal
class IOBUF extends BlackBox {
val io = new Bundle {
val O = Output(Bool())
val IO = Analog(1.W)
val I = Input(Bool())
val T = Input(Bool())
}
}
object IOBUF {
def apply (pin: Analog, ctrl: BasePin): Bool = {
val pad = Module(new IOBUF())
pad.io.I := ctrl.o.oval
pad.io.T := ~ctrl.o.oe
ctrl.i.ival := pad.io.O & ctrl.o.ie
attach(pad.io.IO, pin)
pad.io.O & ctrl.o.ie
}
// Creates an output IOBUF
def apply (pin: Analog, in: Bool): Unit = {
val pad = Module(new IOBUF())
pad.io.I := in
pad.io.T := false.B
attach(pad.io.IO, pin)
}
// Creates an input IOBUF
def apply (pin: Analog): Bool = {
val pad = Module(new IOBUF())
pad.io.I := false.B
pad.io.T := true.B
attach(pad.io.IO, pin)
pad.io.O
}
}
/** ODDR - 7 Series SelectIO DDR flop */
class ODDR(
DDR_CLK_EDGE : String = "OPPOSITE_EDGE",
INIT : Boolean = false,
IS_C_INVERTED : Boolean = false,
IS_D1_INVERTED : Boolean = false,
IS_D2_INVERTED : Boolean = false,
SRTYPE : String = "SYNC"
)
extends BlackBox(
Map(
"DDR_CLK_EDGE" -> StringParam(DDR_CLK_EDGE),
"INIT" -> booleanToVerilogVectorParam(INIT),
"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
"IS_D1_INVERTED" -> booleanToVerilogVectorParam(IS_D1_INVERTED),
"IS_D2_INVERTED" -> booleanToVerilogVectorParam(IS_D2_INVERTED),
"SRTYPE" -> StringParam(SRTYPE)
)
) {
val io = IO(new Bundle {
val Q = Output(Bool())
val C = Input(Bool())
val CE = Input(Bool())
val D1 = Input(Bool())
val D2 = Input(Bool())
val R = Input(Bool())
val S = Input(Bool())
})
}
/** ODELAYE2 -- 7 Series SelectIO OLogic programmable delay. */
class ODELAYE2(
CINVCTRL_SEL : Boolean = false,
DELAY_SRC : String = "ODATAIN",
HIGH_PERFORMANCE_MODE : Boolean = false,
IS_C_INVERTED : Boolean = false,
IS_ODATAIN_INVERTED : Boolean = false,
ODELAY_TYPE : String = "FIXED",
ODELAY_VALUE : Int = 0,
PIPE_SEL : Boolean = false,
REFCLK_FREQUENCY : Double = 200.0,
SIGNAL_PATTERN : String = "DATA",
SIM_DELAY_D : Int = 0
)
extends BlackBox(
Map(
"CINVCTRL_SEL" -> booleanToVerilogStringParam(CINVCTRL_SEL),
"DELAY_SRC" -> StringParam(DELAY_SRC),
"HIGH_PERFORMANCE_MODE" -> booleanToVerilogStringParam(HIGH_PERFORMANCE_MODE),
"IS_C_INVERTED" -> booleanToVerilogVectorParam(IS_C_INVERTED),
"IS_ODATAIN_INVERTED" -> booleanToVerilogVectorParam(IS_ODATAIN_INVERTED),
"ODELAY_TYPE" -> StringParam(ODELAY_TYPE),
"PIPE_SEL" -> booleanToVerilogStringParam(PIPE_SEL),
"REFCLK_FREQUENCY" -> DoubleParam(REFCLK_FREQUENCY),
"SIGNAL_PATTERN" -> StringParam(SIGNAL_PATTERN),
"SIM_DELAY_D" -> IntParam(SIM_DELAY_D)
)
) {
val io = IO(new Bundle {
val DATAOUT = Output(Bool())
val CNTVALUEOUT = Output(UInt(5.W))
val C = Input(Bool())
val CE = Input(Bool())
val CINVCTRL = Input(Bool())
val CLKIN = Input(Bool())
val INC = Input(Bool())
val LD = Input(Bool())
val LDPIPEEN = Input(Bool())
val ODATAIN = Input(Bool())
val REGRST = Input(Bool())
val CNTVALUEIN = Input(UInt(5.W))
})
}
/** PULLUP : can be applied to Input to add a Pullup. */
class PULLUP extends BlackBox {
val io = IO(new Bundle {
val O = Analog(1.W)
})
}
object PULLUP {
def apply (pin: Analog): Unit = {
val pullup = Module(new PULLUP())
attach(pullup.io.O, pin)
}
}

189
src/main/scala/ip/xilinx/Xilinx.scala
View File

@ -13,99 +13,6 @@ import sifive.blocks.devices.pinctrl.{BasePin}
// BlackBox modules used in the Xilinx FPGA flows
//========================================================================
//-------------------------------------------------------------------------
// IBUFDS
//-------------------------------------------------------------------------
//IP : xilinx unisim IBUFDS. SelectIO Differential Signaling Input
// Buffer unparameterized
class IBUFDS extends BlackBox {
val io = new Bundle {
val O = Bool(OUTPUT)
val I = Bool(INPUT)
val IB = Bool(INPUT)
}
}
//-------------------------------------------------------------------------
// IBUFG
//-------------------------------------------------------------------------
/** IBUFG -- Clock Input Buffer */
class IBUFG extends BlackBox {
val io = new Bundle {
val O = Output(Clock())
val I = Input(Clock())
}
}
object IBUFG {
def apply (pin: Clock): Clock = {
val pad = Module (new IBUFG())
pad.io.I := pin
pad.io.O
}
}
//-------------------------------------------------------------------------
// IOBUF
//-------------------------------------------------------------------------
/** IOBUF -- Bidirectional IO Buffer. */
class IOBUF extends BlackBox {
val io = new Bundle {
val O = Output(Bool())
val IO = Analog(1.W)
val I = Input(Bool())
val T = Input(Bool())
}
}
object IOBUF {
def apply (pin: Analog, ctrl: BasePin): Bool = {
val pad = Module(new IOBUF())
pad.io.I := ctrl.o.oval
pad.io.T := ~ctrl.o.oe
ctrl.i.ival := pad.io.O & ctrl.o.ie
attach(pad.io.IO, pin)
pad.io.O & ctrl.o.ie
}
// Creates an output IOBUF
def apply (pin: Analog, in: Bool): Unit = {
val pad = Module(new IOBUF())
pad.io.I := in
pad.io.T := false.B
attach(pad.io.IO, pin)
}
// Creates an input IOBUF
def apply (pin: Analog): Bool = {
val pad = Module(new IOBUF())
pad.io.I := false.B
pad.io.T := true.B
attach(pad.io.IO, pin)
pad.io.O
}
}
//-------------------------------------------------------------------------
// PULLUP
//-------------------------------------------------------------------------
/** PULLUP : can be applied to Input to add a Pullup. */
class PULLUP extends BlackBox {
val io = new Bundle {
val O = Analog(1.W)
}
}
object PULLUP {
def apply (pin: Analog): Unit = {
val pullup = Module(new PULLUP())
attach(pullup.io.O, pin)
}
}
//-------------------------------------------------------------------------
// mmcm
@ -303,6 +210,102 @@ class vc707_sys_clock_mmcm1 extends BlackBox {
)
}
class vc707_sys_clock_mmcm2 extends BlackBox {
val io = new Bundle {
val clk_in1 = Bool(INPUT)
val clk_out1 = Clock(OUTPUT)
val clk_out2 = Clock(OUTPUT)
val clk_out3 = Clock(OUTPUT)
val clk_out4 = Clock(OUTPUT)
val clk_out5 = Clock(OUTPUT)
val clk_out6 = Clock(OUTPUT)
val clk_out7 = Clock(OUTPUT)
val reset = Bool(INPUT)
val locked = Bool(OUTPUT)
}
ElaborationArtefacts.add(
"vc707_sys_clock_mmcm2.vivado.tcl",
"""create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm2 -dir $ipdir -force
set_property -dict [list \
CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.CLKOUT1_USED {true} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_USED {true} \
CONFIG.CLKOUT6_USED {true} \
CONFIG.CLKOUT7_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {37.5} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {100} \
CONFIG.CLKOUT7_REQUESTED_PHASE {180} \
CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.PRIM_IN_FREQ {200.000} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
CONFIG.MMCM_DIVCLK_DIVIDE {2} \
CONFIG.MMCM_CLKFBOUT_MULT_F {9.0} \
CONFIG.MMCM_CLKIN1_PERIOD {5.0} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {72.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {36} \
CONFIG.MMCM_CLKOUT2_DIVIDE {24} \
CONFIG.MMCM_CLKOUT3_DIVIDE {18} \
CONFIG.MMCM_CLKOUT4_DIVIDE {9} \
CONFIG.MMCM_CLKOUT5_DIVIDE {6} \
CONFIG.MMCM_CLKOUT6_DIVIDE {9} \
CONFIG.NUM_OUT_CLKS {7} \
CONFIG.CLKOUT1_JITTER {206.010} \
CONFIG.CLKOUT1_PHASE_ERROR {105.461} \
CONFIG.CLKOUT2_JITTER {180.172} \
CONFIG.CLKOUT2_PHASE_ERROR {105.461} \
CONFIG.CLKOUT3_JITTER {166.503} \
CONFIG.CLKOUT3_PHASE_ERROR {105.461} \
CONFIG.CLKOUT4_JITTER {157.199} \
CONFIG.CLKOUT4_PHASE_ERROR {105.461} \
CONFIG.CLKOUT5_JITTER {136.686} \
CONFIG.CLKOUT5_PHASE_ERROR {105.461} \
CONFIG.CLKOUT6_JITTER {126.399} \
CONFIG.CLKOUT6_PHASE_ERROR {105.461} \
CONFIG.CLKOUT7_JITTER {206.010} \
CONFIG.CLKOUT7_PHASE_ERROR {136.686}] [get_ips vc707_sys_clock_mmcm2] """
)
}
class vc707_sys_clock_mmcm3 extends BlackBox {
val io = new Bundle {
val clk_in1 = Bool(INPUT)
val clk_out1 = Clock(OUTPUT)
val reset = Bool(INPUT)
val locked = Bool(OUTPUT)
}
ElaborationArtefacts.add(
"vc707_sys_clock_mmcm3.vivado.tcl",
"""create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm3 -dir $ipdir -force
set_property -dict [list \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.PRIM_IN_FREQ {100} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \
CONFIG.CLKOUT1_REQUESTED_PHASE {180} \
CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.CLKIN1_JITTER_PS {100.0} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
CONFIG.MMCM_CLKIN1_PERIOD {10.0} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {10} \
CONFIG.MMCM_CLKOUT1_PHASE {180.000} \
CONFIG.NUM_OUT_CLKS {1} \
CONFIG.CLKOUT1_JITTER {130.958} \
CONFIG.CLKOUT1_PHASE_ERROR {98.575}] [get_ips vc707_sys_clock_mmcm3] """
)
}
//-------------------------------------------------------------------------
// vc707reset
//-------------------------------------------------------------------------

14
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
View File

@ -193,7 +193,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
address = List(AddressSet(0x40000000L, 0x1fffffffL)),
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 128),
@ -202,7 +202,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0
resources = device.reg("control"),
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
@ -402,13 +402,13 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
"""
create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
set_property -dict [list \
CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \
CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
CONFIG.AXIBAR_0 {0x60000000} \
CONFIG.AXIBAR_0 {0x40000000} \
CONFIG.AXIBAR_1 {0xFFFFFFFF} \
CONFIG.AXIBAR_2 {0xFFFFFFFF} \
CONFIG.AXIBAR_3 {0xFFFFFFFF} \
@ -420,7 +420,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
CONFIG.AXIBAR_AS_3 {false} \
CONFIG.AXIBAR_AS_4 {false} \
CONFIG.AXIBAR_AS_5 {false} \
CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \
CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
@ -440,14 +440,14 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
CONFIG.BAR2_SIZE {8} \
CONFIG.BAR2_TYPE {N/A} \
CONFIG.BAR_64BIT {true} \
CONFIG.BASEADDR {0x50000000} \
CONFIG.BASEADDR {0x00000000} \
CONFIG.BASE_CLASS_MENU {Bridge_device} \
CONFIG.CLASS_CODE {0x060400} \
CONFIG.COMP_TIMEOUT {50ms} \
CONFIG.Component_Name {design_1_axi_pcie_1_0} \
CONFIG.DEVICE_ID {0x7111} \
CONFIG.ENABLE_CLASS_CODE {true} \
CONFIG.HIGHADDR {0x53FFFFFF} \
CONFIG.HIGHADDR {0x03FFFFFF} \
CONFIG.INCLUDE_BAROFFSET_REG {true} \
CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
CONFIG.INTERRUPT_PIN {false} \

96
src/main/scala/shell/xilinx/VC707Shell.scala
View File

@ -7,7 +7,7 @@ import chisel3.experimental.{RawModule, Analog, withClockAndReset}
import freechips.rocketchip.config._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg}
import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg, ElaborationArtefacts}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
@ -16,7 +16,7 @@ import sifive.blocks.devices.uart._
import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, vc707_sys_clock_mmcm0,
vc707_sys_clock_mmcm1, vc707reset}
vc707_sys_clock_mmcm1, vc707_sys_clock_mmcm2 , vc707reset}
//-------------------------------------------------------------------------
// VC707Shell
@ -55,6 +55,72 @@ trait HasPCIe { this: VC707Shell =>
}
}
trait HasDebugJTAG { this: VC707Shell =>
// JTAG
val jtag_TCK = IO(Input(Clock()))
val jtag_TMS = IO(Input(Bool()))
val jtag_TDI = IO(Input(Bool()))
val jtag_TDO = IO(Output(Bool()))
def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
ElaborationArtefacts.add(
"""debugjtag.vivado.tcl""",
"""set vc707debugjtag_vivado_tcl_dir [file dirname [file normalize [info script]]]
add_files -fileset [current_fileset -constrset] [glob -directory $vc707debugjtag_vivado_tcl_dir {*.vc707debugjtag.xdc}]"""
)
if(fmcxm105) {
//VC707 constraints for Xilinx FMC XM105 Debug Card
ElaborationArtefacts.add(
"""vc707debugjtag.xdc""",
"""set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
)
} else {
//VC707 constraints for Olimex connect to LCD panel header
ElaborationArtefacts.add(
"""vc707debugjtag.xdc""",
"""
#Olimex Pin Olimex Function LCD Pin LCD Function FPGA Pin
#1 VREF 14 5V
#3 TTRST_N 1 LCD_DB7 AN40
#5 TTDI 2 LCD_DB6 AR39
#7 TTMS 3 LCD_DB5 AR38
#9 TTCK 4 LCD_DB4 AT42
#11 TRTCK NC NC NC
#13 TTDO 9 LCD_E AT40
#15 TSRST_N 10 LCD_RW AR42
#2 VREF 14 5V
#18 GND 13 GND
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
set_property -dict { PACKAGE_PIN AT42 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
set_property -dict { PACKAGE_PIN AR38 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
set_property -dict { PACKAGE_PIN AR39 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
set_property -dict { PACKAGE_PIN AT40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
)
}
val djtag = dut.debug.systemjtag.get
djtag.jtag.TCK := jtag_TCK
djtag.jtag.TMS := jtag_TMS
djtag.jtag.TDI := jtag_TDI
jtag_TDO := djtag.jtag.TDO.data
djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
djtag.reset := PowerOnResetFPGAOnly(dut_clock)
dut_ndreset := dut.debug.ndreset
djtag
}
}
abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
//-----------------------------------------------------------------------
@ -82,12 +148,6 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
val sdio_cmd = IO(Analog(1.W))
val sdio_dat = IO(Analog(4.W))
// JTAG
val jtag_TCK = IO(Input(Clock()))
val jtag_TMS = IO(Input(Bool()))
val jtag_TDI = IO(Input(Bool()))
val jtag_TDO = IO(Output(Bool()))
//Buttons
val btn_0 = IO(Analog(1.W))
val btn_1 = IO(Analog(1.W))
@ -163,7 +223,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
//-----------------------------------------------------------------------
//25MHz and multiples
val vc707_sys_clock_mmcm0 = Module(new vc707_sys_clock_mmcm0)
val vc707_sys_clock_mmcm0 = Module(new vc707_sys_clock_mmcm2)
vc707_sys_clock_mmcm0.io.clk_in1 := sys_clock.asUInt
vc707_sys_clock_mmcm0.io.reset := reset
val clk12_5 = vc707_sys_clock_mmcm0.io.clk_out1
@ -173,6 +233,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
val clk100 = vc707_sys_clock_mmcm0.io.clk_out5
val clk150 = vc707_sys_clock_mmcm0.io.clk_out6
val clk75 = vc707_sys_clock_mmcm0.io.clk_out7
val clk100_180 = vc707_sys_clock_mmcm0.io.clk_out7
val vc707_sys_clock_mmcm0_locked = vc707_sys_clock_mmcm0.io.locked
//65MHz and multiples
@ -218,24 +279,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
mig_mmcm_locked := UInt("b1")
mmcm_lock_pcie := UInt("b1")
//---------------------------------------------------------------------
// Debug JTAG
//---------------------------------------------------------------------
def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): SystemJTAGIO = {
val djtag = dut.debug.systemjtag.get
djtag.jtag.TCK := jtag_TCK
djtag.jtag.TMS := jtag_TMS
djtag.jtag.TDI := jtag_TDI
jtag_TDO := djtag.jtag.TDO.data
djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
djtag.reset := PowerOnResetFPGAOnly(dut_clock)
dut_ndreset := dut.debug.ndreset
djtag
}
//-----------------------------------------------------------------------
// UART

28
xilinx/vc707/constraints/vc707-master.xdc
View File

@ -64,13 +64,6 @@ set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}]
set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}]
set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}]
# JTAG
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
# SDIO
set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
@ -79,18 +72,23 @@ set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
set_clock_groups -asynchronous \
-group { clk_pll_i } \
-group { \
clk_out1_vc707_sys_clock_mmcm0 \
clk_out2_vc707_sys_clock_mmcm0 \
clk_out3_vc707_sys_clock_mmcm0 \
clk_out4_vc707_sys_clock_mmcm0 \
clk_out5_vc707_sys_clock_mmcm0 \
clk_out6_vc707_sys_clock_mmcm0 \
clk_out7_vc707_sys_clock_mmcm0 } \
sys_diff_clk \
clk_out1_vc707_sys_clock_mmcm2 \
clk_out2_vc707_sys_clock_mmcm2 \
clk_out3_vc707_sys_clock_mmcm2 \
clk_out4_vc707_sys_clock_mmcm2 \
clk_out5_vc707_sys_clock_mmcm2 \
clk_out6_vc707_sys_clock_mmcm2 \
clk_out7_vc707_sys_clock_mmcm2 } \
-group { \
clk_out1_vc707_sys_clock_mmcm1 \
clk_out2_vc707_sys_clock_mmcm1 } \
-group { \
clk_out1_vc707_sys_clock_mmcm3 \
chiplink_b2c_clock } \
-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]