riscv/fpga-shells
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Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
31 Commits 2 Branches 0 Tags 682 KiB
Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%
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Wesley W. Terpstra 8b0d7ec91a
TransferSizes: just because a device CAN do more does not mean it should (#15) 
Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
src/main/scala TransferSizes: just because a device CAN do more does not mean it should (#15) 2017-12-10 00:42:11 -08:00
xilinx VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock 2017-11-01 14:23:07 -07:00
.gitignore Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00