Merge pull request #8 from sifive/replace-env-vars-with-cli-args

Restructure Tcl script entrypoint.

xilinx/common/tcl/init.tcl

@@ -10,8 +10,8 @@ file mkdir $ipdir
 update_ip_catalog -rebuild
 
 # Generate IP implementations. Vivado TCL emitted from Chisel Blackboxes
-foreach ipvivadotcl $ipvivadotcls {
-  source $ipvivadotcl
+foreach ip_vivado_tcl $ip_vivado_tcls {
+  source $ip_vivado_tcl
 }
 # Optional board-specific ip script
 set boardiptcl [file join $boarddir tcl ip.tcl]

xilinx/common/tcl/prologue.tcl

@@ -1,13 +1,55 @@
 # See LICENSE for license details.
 
-# Set the variable for the directory that includes all scripts
-set scriptdir [file dirname [info script]]
+# Process command line arguments
+# http://wiki.tcl.tk/1730
+set ip_vivado_tcls {}
+
+while {[llength $argv]} {
+  set argv [lassign $argv[set argv {}] flag]
+  switch -glob $flag {
+    -top-module {
+      set argv [lassign $argv[set argv {}] top]
+    }
+    -F {
+      # This should be a simple file format with one filepath per line
+      set argv [lassign $argv[set argv {}] vsrc_manifest]
+    }
+    -board {
+      set argv [lassign $argv[set argv {}] board]
+    }
+    -ip-vivado-tcls {
+      set argv [lassign $argv[set argv {}] ip_vivado_tcls]
+    }
+    -pre-impl-debug-tcl {
+      set argv [lassign $argv[set argv {}] pre_impl_debug_tcl]
+    }
+    -post-impl-debug-tcl {
+      set argv [lassign $argv[set argv {}] post_impl_debug_tcl]
+    }
+    default {
+      return -code error [list {unknown option} $flag]
+    }
+  }
+}
+
+if {![info exists top]} {
+  return -code error [list {--top-module option is required}]
+}
+
+if {![info exists vsrc_manifest]} {
+  return -code error [list {-F option is required}]
+}
+
+if {![info exists board]} {
+  return -code error [list {--board option is required}]
+}
 
 # Set the variable for all the common files
 set commondir [file dirname $scriptdir]
 
 # Set the variable that points to board specific files
-set boarddir [file join [file dirname $commondir] $name]
+set boarddir [file join [file dirname $commondir] $board]
+source [file join $boarddir tcl board.tcl]
 
 # Set the variable that points to board constraint files
 set constraintsdir [file join $boarddir constraints]
@@ -21,9 +63,6 @@ set wrkdir [file join [pwd] obj]
 # Create the directory for IPs
 set ipdir [file join $wrkdir ip]
 
-# Set the top for the design based on an environment variable
-set top $::env(FPGA_TOP_SYSTEM)
-
 # Create an in-memory project
 create_project -part $part_fpga -in_memory
 
@@ -41,16 +80,29 @@ if {[get_filesets -quiet sources_1] eq ""} {
 }
 set obj [current_fileset]
 
-# Add verilog files TCL from VSRCSVIVADOTCL environment variable
-if {[info exists ::env(VSRCSVIVADOTCL)]} {
-  source $::env(VSRCSVIVADOTCL)
+# Add verilog files from manifest
+proc load_vsrc_manifest {obj vsrc_manifest} {
+  set fp [open $vsrc_manifest r]
+  set files [lsearch -not -exact -all -inline [split [read $fp] "\n"] {}]
+  set relative_files {}
+  foreach path $files {
+    if {[string match {/*} $path]} {
+      lappend relative_files $path
+    } elseif {![string match {#*} $path]} {
+      lappend relative_files [file join [file dirname $vsrc_manifest] $path]
+    }
+  }
+  add_files -norecurse -fileset $obj {*}$relative_files
+  close $fp
 }
 
-# Add IP Vivado TCL from IPVIVADOTCL environment variable
-if {[info exists ::env(IPVIVADOTCLS)]} {
+load_vsrc_manifest $obj $vsrc_manifest
+
+# Add IP Vivado TCL
+if {$ip_vivado_tcls ne {}} {
   # Split string into words even with multiple consecutive spaces
   # http://wiki.tcl.tk/989
-  set ipvivadotcls [regexp -inline -all -- {\S+} $::env(IPVIVADOTCLS)]
+  set ip_vivado_tcls [regexp -inline -all -- {\S+} $ip_vivado_tcls]
 }
 
 if {[get_filesets -quiet sim_1] eq ""} {

xilinx/common/tcl/vivado.tcl

@@ -1,11 +1,20 @@
 # See LICENSE for license details.
 
+# Set the variable for the directory that includes all scripts
+set scriptdir [file dirname [info script]]
+
+# Set up variables and Vivado objects
+source [file join $scriptdir "prologue.tcl"]
+
+# Initialize Vivado project files
+source [file join $scriptdir "init.tcl"]
+
 # Synthesize the design
 source [file join $scriptdir "synth.tcl"]
 
 # Pre-implementation debug
-if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} {
-  source [file join $scriptdir $::env(PRE_IMPL_DEBUG_TCL)]
+if {[info exists pre_impl_debug_tcl]} {
+  source [file join $scriptdir $pre_impl_debug_tcl]
 }
 
 # Post synthesis optimization
@@ -21,8 +30,8 @@ source [file join $scriptdir "route.tcl"]
 source [file join $scriptdir "bitstream.tcl"]
 
 # Post-implementation debug
-if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} {
-  source [file join $scriptdir $::env(POST_IMPL_DEBUG_TCL)]
+if {[info exists post_impl_debug_tcl)]} {
+  source [file join $scriptdir $post_impl_debug_tcl]
 }
 
 # Create reports for the current implementation