Wesley W. TerpstraandGitHub 6df6db25de Merge pull request #18 from sifive/dynamic-clock-groups ...

Dynamic clock groups -- fixes timing closure problem for vc707 designs without ChipLink

2018-02-25 15:08:15 -08:00

src/main/scala

vc707: setup 100MHz PLL

2018-02-08 07:21:45 -08:00

xilinx

vc707: add clock groups dynamically iff they exist

2018-02-25 14:33:32 -08:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%