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riscv
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fpga-shells
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Freedom FPGA mappings (
https://github.com/sifive/fpga-shells
)
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682
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Scala
89.5%
Tcl
7.8%
Verilog
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Makefile
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33c88b8cc4
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Henry Styles
33c88b8cc4
Move Xilinx unisims into separate file
2018-02-08 07:21:44 -08:00
src/main
/scala
Move Xilinx unisims into separate file
2018-02-08 07:21:44 -08:00
xilinx
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
2017-11-01 14:23:07 -07:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00