riscv/fpga-shells
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Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
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Scala 89.5%
Tcl 7.8%
Verilog 2%
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Henry Cook 0ca9f2bb66
periphery: bus api update (#17) 
* periphery: bus api update

* Update XilinxVC707MIGPeriphery.scala
2018-03-01 01:16:04 -08:00
src/main/scala periphery: bus api update (#17) 2018-03-01 01:16:04 -08:00
xilinx prologue: support the absence of an xdc/tcl constraint file 2018-02-25 15:21:03 -08:00
.gitignore Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00