This website requires JavaScript.
Explore
Help
Sign In
riscv
/
fpga-shells
Watch
1
Star
0
Fork
0
You've already forked fpga-shells
Code
Releases
Activity
45
Commits
2
Branches
0
Tags
0ca9f2bb66a8987b3334e446c27e05c7c2c6bde9
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Henry Cook
0ca9f2bb66
periphery: bus api update (
#17
)
...
* periphery: bus api update * Update XilinxVC707MIGPeriphery.scala
2018-03-01 01:16:04 -08:00
src/main
/scala
periphery: bus api update (
#17
)
2018-03-01 01:16:04 -08:00
xilinx
prologue: support the absence of an xdc/tcl constraint file
2018-02-25 15:21:03 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
Description
Freedom FPGA mappings (
https://github.com/sifive/fpga-shells
)
682
KiB
Languages
Scala
89.5%
Tcl
7.8%
Verilog
2%
Makefile
0.7%