Merge pull request #14 from sifive/vc707_mig_pcie_traits
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits
This commit is contained in:
Henry Styles
GitHub
commit
ba7beb676d
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@ -188,11 +188,11 @@ object PowerOnResetFPGAOnly {
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}
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//-------------------------------------------------------------------------
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// vc707clk_wiz_sync
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// vc707_sys_clock_mmcm
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//-------------------------------------------------------------------------
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//IP : xilinx mmcm with "NO_BUFFER" input clock
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class vc707clk_wiz_sync extends BlackBox {
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class vc707_sys_clock_mmcm0 extends BlackBox {
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val io = new Bundle {
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val clk_in1 = Bool(INPUT)
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val clk_out1 = Clock(OUTPUT)
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@ -207,8 +207,8 @@ class vc707clk_wiz_sync extends BlackBox {
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}
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ElaborationArtefacts.add(
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"vc707clk_wiz_sync.vivado.tcl",
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"""create_ip -name clk_wiz -vendor xilinx.com -library ip -version 5.3 -module_name vc707clk_wiz_sync -dir $ipdir -force
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"vc707_sys_clock_mmcm0.vivado.tcl",
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"""create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm0 -dir $ipdir -force
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set_property -dict [list \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_SOURCE {No_buffer} \
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@ -252,7 +252,54 @@ class vc707clk_wiz_sync extends BlackBox {
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CONFIG.CLKOUT6_JITTER {102.207} \
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CONFIG.CLKOUT6_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT7_JITTER {117.249} \
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CONFIG.CLKOUT7_PHASE_ERROR {91.235}] [get_ips vc707clk_wiz_sync] """
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CONFIG.CLKOUT7_PHASE_ERROR {91.235}] [get_ips vc707_sys_clock_mmcm0] """
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)
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}
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class vc707_sys_clock_mmcm1 extends BlackBox {
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val io = new Bundle {
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val clk_in1 = Bool(INPUT)
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val clk_out1 = Clock(OUTPUT)
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val clk_out2 = Clock(OUTPUT)
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val reset = Bool(INPUT)
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val locked = Bool(OUTPUT)
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}
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ElaborationArtefacts.add(
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"vc707_sys_clock_mmcm1.vivado.tcl",
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"""create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm1 -dir $ipdir -force
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set_property -dict [list \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_SOURCE {No_buffer} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {false} \
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CONFIG.CLKOUT4_USED {false} \
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CONFIG.CLKOUT5_USED {false} \
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CONFIG.CLKOUT6_USED {false} \
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CONFIG.CLKOUT7_USED {false} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {32.5} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65} \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_IN_FREQ {200.000} \
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CONFIG.CLKIN1_JITTER_PS {50.0} \
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CONFIG.MMCM_DIVCLK_DIVIDE {1} \
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CONFIG.MMCM_CLKFBOUT_MULT_F {4.875} \
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CONFIG.MMCM_CLKIN1_PERIOD {5.0} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {30.000} \
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CONFIG.MMCM_CLKOUT1_DIVIDE {15} \
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CONFIG.MMCM_CLKOUT2_DIVIDE {1} \
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CONFIG.MMCM_CLKOUT3_DIVIDE {1} \
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CONFIG.MMCM_CLKOUT4_DIVIDE {1} \
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CONFIG.MMCM_CLKOUT5_DIVIDE {1} \
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CONFIG.MMCM_CLKOUT6_DIVIDE {1} \
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CONFIG.NUM_OUT_CLKS {2} \
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CONFIG.CLKOUT1_JITTER {135.973} \
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CONFIG.CLKOUT1_PHASE_ERROR {87.159} \
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CONFIG.CLKOUT2_JITTER {117.878} \
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CONFIG.CLKOUT2_PHASE_ERROR {87.159} \
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CONFIG.CLKOUT3_JITTER {131.973} \
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CONFIG.CLKOUT3_PHASE_ERROR {87.159}] \
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[get_ips vc707_sys_clock_mmcm1] """
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)
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}
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@ -15,18 +15,52 @@ import sifive.blocks.devices.uart._
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, vc707clk_wiz_sync, vc707reset}
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import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, vc707_sys_clock_mmcm0,
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vc707_sys_clock_mmcm1, vc707reset}
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//-------------------------------------------------------------------------
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// VC707Shell
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//-------------------------------------------------------------------------
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trait HasDDR3 { this: VC707Shell =>
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require(!p.lift(MemoryXilinxDDRKey).isEmpty)
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val ddr = IO(new XilinxVC707MIGPads(p(MemoryXilinxDDRKey)))
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def connectMIG(dut: HasMemoryXilinxVC707MIGModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707mig.sys_clk_i := sys_clock.asUInt
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mig_clock := dut.xilinxvc707mig.ui_clk
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mig_sys_reset := dut.xilinxvc707mig.ui_clk_sync_rst
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mig_mmcm_locked := dut.xilinxvc707mig.mmcm_locked
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dut.xilinxvc707mig.aresetn := mig_resetn
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dut.xilinxvc707mig.sys_rst := sys_reset
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ddr <> dut.xilinxvc707mig
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}
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}
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trait HasPCIe { this: VC707Shell =>
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val pcie = IO(new XilinxVC707PCIeX1Pads)
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def connectPCIe(dut: HasSystemXilinxVC707PCIeX1ModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
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pcie_dat_clock := dut.xilinxvc707pcie.axi_aclk_out
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pcie_cfg_clock := dut.xilinxvc707pcie.axi_ctl_aclk_out
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mmcm_lock_pcie := dut.xilinxvc707pcie.mmcm_lock
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dut.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
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pcie <> dut.xilinxvc707pcie
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}
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}
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abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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//-----------------------------------------------------------------------
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// Interface
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//-----------------------------------------------------------------------
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// 200Mhz differential sysclk
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val sys_diff_clock_clk_n = IO(Input(Bool()))
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val sys_diff_clock_clk_p = IO(Input(Bool()))
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@ -34,9 +68,6 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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// active high reset
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val reset = IO(Input(Bool()))
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// DDR SDRAM
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val ddr = IO(new XilinxVC707MIGPads(p(MemoryXilinxDDRKey)))
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// LED
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val led = IO(Vec(8, Output(Bool())))
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@ -57,8 +88,22 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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val jtag_TDI = IO(Input(Bool()))
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val jtag_TDO = IO(Output(Bool()))
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// PCIe
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val pcie = IO(new XilinxVC707PCIeX1Pads)
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//Buttons
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val btn_0 = IO(Analog(1.W))
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val btn_1 = IO(Analog(1.W))
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val btn_2 = IO(Analog(1.W))
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val btn_3 = IO(Analog(1.W))
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//Sliding switches
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val sw_0 = IO(Analog(1.W))
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val sw_1 = IO(Analog(1.W))
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val sw_2 = IO(Analog(1.W))
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val sw_3 = IO(Analog(1.W))
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val sw_4 = IO(Analog(1.W))
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val sw_5 = IO(Analog(1.W))
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val sw_6 = IO(Analog(1.W))
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val sw_7 = IO(Analog(1.W))
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//-----------------------------------------------------------------------
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// Wire declrations
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@ -117,18 +162,26 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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// Clock Generator
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//-----------------------------------------------------------------------
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val coreplex_mmcm = Module(new vc707clk_wiz_sync)
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coreplex_mmcm.io.clk_in1 := sys_clock.asUInt
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coreplex_mmcm.io.reset := mig_sys_reset
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//25MHz and multiples
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val vc707_sys_clock_mmcm0 = Module(new vc707_sys_clock_mmcm0)
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vc707_sys_clock_mmcm0.io.clk_in1 := sys_clock.asUInt
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vc707_sys_clock_mmcm0.io.reset := reset
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val clk12_5 = vc707_sys_clock_mmcm0.io.clk_out1
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val clk25 = vc707_sys_clock_mmcm0.io.clk_out2
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val clk37_5 = vc707_sys_clock_mmcm0.io.clk_out3
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val clk50 = vc707_sys_clock_mmcm0.io.clk_out4
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val clk100 = vc707_sys_clock_mmcm0.io.clk_out5
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val clk150 = vc707_sys_clock_mmcm0.io.clk_out6
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val clk75 = vc707_sys_clock_mmcm0.io.clk_out7
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val vc707_sys_clock_mmcm0_locked = vc707_sys_clock_mmcm0.io.locked
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val clk12_5 = coreplex_mmcm.io.clk_out1
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val clk25 = coreplex_mmcm.io.clk_out2
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val clk37_5 = coreplex_mmcm.io.clk_out3
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val clk50 = coreplex_mmcm.io.clk_out4
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val clk100 = coreplex_mmcm.io.clk_out5
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val clk150 = coreplex_mmcm.io.clk_out6
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val clk75 = coreplex_mmcm.io.clk_out7
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val coreplex_mmcm_locked = coreplex_mmcm.io.locked
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//65MHz and multiples
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val vc707_sys_clock_mmcm1 = Module(new vc707_sys_clock_mmcm1)
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vc707_sys_clock_mmcm1.io.clk_in1 := sys_clock.asUInt
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vc707_sys_clock_mmcm1.io.reset := reset
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val clk32_5 = vc707_sys_clock_mmcm1.io.clk_out1
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val clk65 = vc707_sys_clock_mmcm1.io.clk_out2
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val vc707_sys_clock_mmcm1_locked = vc707_sys_clock_mmcm1.io.locked
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// DUT clock
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dut_clock := clk37_5
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@ -137,12 +190,14 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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// System reset
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//-----------------------------------------------------------------------
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do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset || !coreplex_mmcm_locked
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do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset || !vc707_sys_clock_mmcm0_locked ||
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!vc707_sys_clock_mmcm1_locked
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mig_resetn := !mig_reset
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dut_resetn := !dut_reset
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pcie_dat_resetn := !pcie_dat_reset
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pcie_cfg_resetn := !pcie_cfg_reset
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val safe_reset = Module(new vc707reset)
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safe_reset.io.areset := do_reset
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@ -155,11 +210,19 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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safe_reset.io.clock4 := dut_clock
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dut_reset := safe_reset.io.reset4
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//overrided in connectMIG and connect PCIe
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//provide defaults to allow above reset sequencing logic to work without both
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mig_clock := dut_clock
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pcie_dat_clock := dut_clock
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pcie_cfg_clock := dut_clock
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mig_mmcm_locked := UInt("b1")
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mmcm_lock_pcie := UInt("b1")
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//---------------------------------------------------------------------
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// Debug JTAG
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//---------------------------------------------------------------------
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): Unit = {
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp): SystemJTAGIO = {
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val djtag = dut.debug.systemjtag.get
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djtag.jtag.TCK := jtag_TCK
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@ -171,6 +234,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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djtag.reset := PowerOnResetFPGAOnly(dut_clock)
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dut_ndreset := dut.debug.ndreset
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djtag
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}
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//-----------------------------------------------------------------------
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@ -224,36 +288,4 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
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ip_sdio_spi.io.spi_dq_o := sd_spi_dq_o.asUInt
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}
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//---------------------------------------------------------------------
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// MIG
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//---------------------------------------------------------------------
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def connectMIG(dut: HasMemoryXilinxVC707MIGModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707mig.sys_clk_i := sys_clock.asUInt
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mig_clock := dut.xilinxvc707mig.ui_clk
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mig_sys_reset := dut.xilinxvc707mig.ui_clk_sync_rst
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mig_mmcm_locked := dut.xilinxvc707mig.mmcm_locked
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dut.xilinxvc707mig.aresetn := mig_resetn
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dut.xilinxvc707mig.sys_rst := sys_reset
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ddr <> dut.xilinxvc707mig
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}
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//---------------------------------------------------------------------
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// PCIE
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//---------------------------------------------------------------------
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def connectPCIe(dut: HasSystemXilinxVC707PCIeX1ModuleImp): Unit = {
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// Clock & Reset
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dut.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
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pcie_dat_clock := dut.xilinxvc707pcie.axi_aclk_out
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pcie_cfg_clock := dut.xilinxvc707pcie.axi_ctl_aclk_out
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mmcm_lock_pcie := dut.xilinxvc707pcie.mmcm_lock
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dut.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
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pcie <> dut.xilinxvc707pcie
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}
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}
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@ -1,5 +1,8 @@
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#---------------Physical Constraints-----------------
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#get_port_part_pins
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#clk_n clk_p dip_switches_tri_i_0 dip_switches_tri_i_1 dip_switches_tri_i_2 dip_switches_tri_i_3 dip_switches_tri_i_4 dip_switches_tri_i_5 dip_switches_tri_i_6 dip_switches_tri_i_7 iic_main_scl_i iic_main_sda_i lcd_7bits_tri_o_0 lcd_7bits_tri_o_1 lcd_7bits_tri_o_2 lcd_7bits_tri_o_3 lcd_7bits_tri_o_4 lcd_7bits_tri_o_5 lcd_7bits_tri_o_6 leds_8bits_tri_o_0 leds_8bits_tri_o_1 leds_8bits_tri_o_2 leds_8bits_tri_o_3 leds_8bits_tri_o_4 leds_8bits_tri_o_5 leds_8bits_tri_o_6 leds_8bits_tri_o_7 linear_flash_addr_1 linear_flash_addr_10 linear_flash_addr_11 linear_flash_addr_12 linear_flash_addr_13 linear_flash_addr_14 linear_flash_addr_15 linear_flash_addr_16 linear_flash_addr_17 linear_flash_addr_18 linear_flash_addr_19 linear_flash_addr_2 linear_flash_addr_20 linear_flash_addr_21 linear_flash_addr_22 linear_flash_addr_23 linear_flash_addr_24 linear_flash_addr_25 linear_flash_addr_26 linear_flash_addr_3 linear_flash_addr_4 linear_flash_addr_5 linear_flash_addr_6 linear_flash_addr_7 linear_flash_addr_8 linear_flash_addr_9 linear_flash_adv_ldn linear_flash_ce_n linear_flash_dq_i_0 linear_flash_dq_i_1 linear_flash_dq_i_10 linear_flash_dq_i_11 linear_flash_dq_i_12 linear_flash_dq_i_13 linear_flash_dq_i_14 linear_flash_dq_i_15 linear_flash_dq_i_2 linear_flash_dq_i_3 linear_flash_dq_i_4 linear_flash_dq_i_5 linear_flash_dq_i_6 linear_flash_dq_i_7 linear_flash_dq_i_8 linear_flash_dq_i_9 linear_flash_oen linear_flash_wen mdc mdio_i phy_rst_out push_buttons_5bits_tri_i_0 push_buttons_5bits_tri_i_1 push_buttons_5bits_tri_i_2 push_buttons_5bits_tri_i_3 push_buttons_5bits_tri_i_4 reset rotary_inca_push_incb_tri_i_0 rotary_inca_push_incb_tri_i_1 rotary_inca_push_incb_tri_i_2 rs232_uart_rxd rs232_uart_txd sfp_rxn sfp_rxp sfp_sgmii_txn sfp_sgmii_txp sgmii_mgt_clkn sgmii_mgt_clkp sgmii_rxn sgmii_rxp sgmii_txn sgmii_txp sma_lvds_rxn sma_lvds_rxp sma_lvds_txn sma_lvds_txp sma_mgt_clkn sma_mgt_clkp sma_sfp_rxn sma_sfp_rxp sma_sfp_txn sma_sfp_txp
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set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
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set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
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set_property BOARD_PIN {reset} [get_ports reset]
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@ -16,6 +19,21 @@ set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led_5]
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set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led_6]
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set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led_7]
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set_property BOARD_PIN {push_buttons_5bits_tri_i_0} [get_ports btn_0]
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set_property BOARD_PIN {push_buttons_5bits_tri_i_1} [get_ports btn_1]
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set_property BOARD_PIN {push_buttons_5bits_tri_i_2} [get_ports btn_2]
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set_property BOARD_PIN {push_buttons_5bits_tri_i_3} [get_ports btn_3]
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set_property BOARD_PIN {push_buttons_5bits_tri_i_4} [get_ports btn_5]
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set_property BOARD_PIN {dip_switches_tri_i_0} [get_ports sw_0]
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set_property BOARD_PIN {dip_switches_tri_i_1} [get_ports sw_1]
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set_property BOARD_PIN {dip_switches_tri_i_2} [get_ports sw_2]
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set_property BOARD_PIN {dip_switches_tri_i_3} [get_ports sw_3]
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set_property BOARD_PIN {dip_switches_tri_i_4} [get_ports sw_4]
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set_property BOARD_PIN {dip_switches_tri_i_5} [get_ports sw_5]
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set_property BOARD_PIN {dip_switches_tri_i_6} [get_ports sw_6]
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set_property BOARD_PIN {dip_switches_tri_i_7} [get_ports sw_7]
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set_property PACKAGE_PIN AU33 [get_ports uart_rx]
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set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
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set_property IOB TRUE [get_ports uart_rx]
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@ -64,11 +82,15 @@ set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
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set_clock_groups -asynchronous \
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-group { clk_pll_i } \
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-group { \
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clk_out1_vc707clk_wiz_sync \
|
||||
clk_out2_vc707clk_wiz_sync \
|
||||
clk_out3_vc707clk_wiz_sync \
|
||||
clk_out4_vc707clk_wiz_sync \
|
||||
clk_out5_vc707clk_wiz_sync \
|
||||
clk_out6_vc707clk_wiz_sync \
|
||||
clk_out7_vc707clk_wiz_sync } \
|
||||
clk_out1_vc707_sys_clock_mmcm0 \
|
||||
clk_out2_vc707_sys_clock_mmcm0 \
|
||||
clk_out3_vc707_sys_clock_mmcm0 \
|
||||
clk_out4_vc707_sys_clock_mmcm0 \
|
||||
clk_out5_vc707_sys_clock_mmcm0 \
|
||||
clk_out6_vc707_sys_clock_mmcm0 \
|
||||
clk_out7_vc707_sys_clock_mmcm0 } \
|
||||
-group { \
|
||||
clk_out1_vc707_sys_clock_mmcm1 \
|
||||
clk_out2_vc707_sys_clock_mmcm1 } \
|
||||
-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue