riscv/fpga-shells
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17e13a3a5078e76483f7c30a3b513507f0c9ebd6
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Wesley W. Terpstra 17e13a3a50 Merge pull request #16 from sifive/chiplink-100 
Chiplink 100
2018-02-08 15:40:16 -08:00
src/main/scala
vc707: setup 100MHz PLL
2018-02-08 07:21:45 -08:00
xilinx
vc707: setup 100MHz PLL
2018-02-08 07:21:45 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
Description
Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
682 KiB
Languages
Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%