riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 3b0c1ed0c3 Cope with changes to AddrMap Andrew Waterman 2016-06-03 13:50:29 -0700
  • cf8be98b2b Cope with changes to AddrMap Andrew Waterman 2016-06-03 13:48:43 -0700
  • 2e88ffc364 Cope with changes to AddrMap Andrew Waterman 2016-06-03 13:47:40 -0700
  • 28161cab45 Merge AddrHashMap and AddrMap Andrew Waterman 2016-06-03 13:46:53 -0700
  • f1745bf142 Allow PLIC nPriorities=0 (priority fixed at 1) Andrew Waterman 2016-06-02 13:48:29 -0700
  • b7ca2145b3 Fix PLIC control bug when !grant.ready Andrew Waterman 2016-06-02 13:47:59 -0700
  • c8338ad809 Instantiate Debug Module (#119) Andrew Waterman 2016-06-02 10:53:41 -0700
  • 0866b4c045 Can't assign to Vec literals Andrew Waterman 2016-06-01 23:36:34 -0700
  • 20e1de08da Avoid chisel2 pitfall Andrew Waterman 2016-06-01 23:35:49 -0700
  • 5629fb62bf Avoid bitwise sub-assignment Andrew Waterman 2016-06-01 21:58:00 -0700
  • 9518b3d589 Fix arithmetic in ROM row count Andrew Waterman 2016-06-01 21:56:24 -0700
  • 8e80d1ec80 Avoid floating-point arithmetic where integers suffice Andrew Waterman 2016-06-01 21:55:46 -0700
  • 13386af1d1 Get rid of unused implicit conversion Andrew Waterman 2016-06-01 19:30:41 -0700
  • 9949347569 First stab at debug interrupts Andrew Waterman 2016-06-01 16:57:10 -0700
  • 11b3cee07a Ahb tweaks (#50) Wesley W. Terpstra 2016-06-01 16:42:39 -0700
  • 695be2f0ae hasti: work-around unsupported 0-width signals Wesley W. Terpstra 2016-06-01 10:47:02 -0700
  • 740a6073f6 Add Debug Module (#49) mwachs5 2016-06-01 16:33:34 -0700
  • 8983b0e865 hopefully the last fix for AXI -> AHB converter Howard Mao 2016-06-01 15:01:52 -0700
  • a917f554fd use Wesley's test SRAM for AXI -> AHB converter test Howard Mao 2016-06-01 11:40:59 -0700
  • 53a0e6cb9c another fix for AXI -> AHB converter Howard Mao 2016-06-01 11:35:17 -0700
  • e8408f0a8a fix HastiRAM Howard Mao 2016-06-01 10:33:59 -0700
  • d0988902f2 fix NASTI -> HASTI bridge Howard Mao 2016-05-31 19:47:50 -0700
  • 8f269b2eec stall for more cycles in Hasti test Howard Mao 2016-05-31 19:46:42 -0700
  • 1311e78d3f Add blocking D$ flush support Andrew Waterman 2016-05-31 19:28:41 -0700
  • 51379621d6 Flush blocking D$ on FENCE.I Andrew Waterman 2016-05-31 19:27:28 -0700
  • 6d82c0d156 Add M_FLUSH_ALL command Andrew Waterman 2016-05-31 19:25:31 -0700
  • 50e3caef36 get rid of Zscale file I missed last time Howard Mao 2016-05-31 14:33:38 -0700
  • 44a216038f Use more generic TileLinkWidthAdapter Andrew Waterman 2016-05-26 22:24:40 -0700
  • 56897f707a Don't rely on Mux1H output when no inputs are hot Andrew Waterman 2016-05-27 12:23:39 -0700
  • 3ee5144923 Fix TLB tag check logic when ASIDs are present Andrew Waterman 2016-05-27 12:24:17 -0700
  • 056d7ec93a Drive hmastlock low in Nasti-Hasti converter Andrew Waterman 2016-05-27 12:23:18 -0700
  • 2a7e7172a9 Update docs for the trace generator Matthew Naylor 2016-05-27 10:54:35 +0100
  • 8afdd7e3da Work around PutBlocks draining into data array prematurely Andrew Waterman 2016-05-26 23:05:44 -0700
  • c104b57c52 Use BitPat implicit conversion in instruction decoder Andrew Waterman 2016-05-26 22:23:21 -0700
  • 96fa1eb6ad Add UInt->BitPat implicit conversion Andrew Waterman 2016-05-26 18:52:08 -0700
  • 10f0e13c25 Use more parsimonious queue depths Andrew Waterman 2016-05-26 18:04:22 -0700
  • 3cc236e9c4 By default, use same TileLink width everywhere Andrew Waterman 2016-05-25 18:01:57 -0700
  • 391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect Andrew Waterman 2016-05-26 16:10:42 -0700
  • 75f06d6e84 Use generic TileLink width adapter Andrew Waterman 2016-05-26 15:59:56 -0700
  • b6d26e90f8 Add generic TileLink width adapter Andrew Waterman 2016-05-26 15:59:42 -0700
  • e036d3a04a Chisel3: gender issue Andrew Waterman 2016-05-26 15:59:08 -0700
  • 8139f71dfb Work around Chisel2 bug Andrew Waterman 2016-05-26 12:37:31 -0700
  • b734beec06 Update build instructions Matthew Naylor 2016-05-26 14:42:26 +0100
  • a2b9d337b6 No need for full-throughput queues in NastiErrorSlave Andrew Waterman 2016-05-26 01:03:40 -0700
  • 2ece3e6102 Use Mem for ReorderQueue data Andrew Waterman 2016-05-26 01:02:56 -0700
  • ddfa30e215 Work around zero-width wire limitations Andrew Waterman 2016-05-26 00:48:46 -0700
  • 0c50bfcfb3 Work around more zero-width wire cases Andrew Waterman 2016-05-25 21:47:48 -0700
  • 22568de5f3 Work around another zero-width wire limitation Andrew Waterman 2016-05-25 21:42:02 -0700
  • e2755a0f0a Work around zero-width wire limitation in HTIF Andrew Waterman 2016-05-25 20:39:53 -0700
  • 3e238adc67 rtc: fix acquire message type check Andrew Waterman 2016-05-25 20:37:48 -0700
  • 40f38dde63 Work around lack of zero-width wires in D$ Andrew Waterman 2016-05-25 19:44:31 -0700
  • 976d4d3184 ahb: AHB parameters should match TileLink parameters by default Wesley W. Terpstra 2016-05-24 15:59:59 -0700
  • ec0d178010 Support M-mode-only implementations Andrew Waterman 2016-05-25 15:40:53 -0700
  • 00ea9a7d82 Remove most of mstatus when user mode isn't supported Andrew Waterman 2016-05-25 15:37:32 -0700
  • 5442b89664 Remove unnecessary muxes in RV32 MulDiv Andrew Waterman 2016-05-25 14:27:02 -0700
  • 9aa724706e Don't include RV64 instructions in RV32 decode table Andrew Waterman 2016-05-25 14:26:45 -0700
  • 7f1792cba3 ahb: backport bridge to chisel2 Wesley W. Terpstra 2016-05-25 12:25:59 -0700
  • da105a5944 Don't allow travis to recurse through submodules Andrew Waterman 2016-05-25 11:21:06 -0700
  • 1c8745dfd2 ahb: backport to chisel2 Wesley W. Terpstra 2016-05-25 11:01:59 -0700
  • da566e7d6a build: use local sbt when building firrtl Wesley W. Terpstra 2016-05-25 11:36:24 -0700
  • e82c080c3c Add blocking D$ Andrew Waterman 2016-05-25 11:08:11 -0700
  • a8462d3cfc bump chisel Andrew Waterman 2016-05-25 11:09:37 -0700
  • 213bb26367 Drive invalidate_lr signal Matthew Naylor 2016-05-25 13:27:12 +0100
  • a9599302bd fix cloneType in nasti.scala (#14) Donggyu 2016-05-24 17:10:17 -0700
  • 5bc78aba99 Merge pull request #15 from terpstra/ahb Andrew Waterman 2016-05-24 17:06:03 -0700
  • c49cb10c74 Merge pull request #42 from terpstra/ahb Andrew Waterman 2016-05-24 17:02:15 -0700
  • 4605b616c1 Fix bug in D$ AMO/storegen logic Andrew Waterman 2016-05-24 16:26:07 -0700
  • 88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches Andrew Waterman 2016-05-24 15:46:51 -0700
  • 5dac7b818d Support set associativity in blocking D$ Andrew Waterman 2016-05-24 15:45:52 -0700
  • e0addb5723 Support uncached AMOs in blocking D$ Andrew Waterman 2016-05-24 15:45:35 -0700
  • f14d87e327 Support larger I$ sets when VM is disabled Andrew Waterman 2016-05-23 17:51:08 -0700
  • 3b35c7470e Add uncached support to blocking D$ Andrew Waterman 2016-05-23 15:42:56 -0700
  • 42f079ce57 JAL requires DW_XPR Andrew Waterman 2016-05-23 14:11:24 -0700
  • b92c73e361 Add LR/SC to blocking D$ Andrew Waterman 2016-05-22 17:18:26 -0700
  • 0d93d1a1a0 Clean up pending store logic a bit Andrew Waterman 2016-05-22 17:17:57 -0700
  • 0b8de578d4 Add additional D$ store buffering to prevent structural hazards Andrew Waterman 2016-05-22 16:16:21 -0700
  • 354cb2d5ec Don't stall I$ response when resolving a branch misprediction Andrew Waterman 2016-05-22 14:08:53 -0700
  • d7790ac6a4 WIP on blocking D$ Andrew Waterman 2016-05-21 16:58:36 -0700
  • 335e2c8a1e Support disabling atomics extension Andrew Waterman 2016-05-21 16:58:01 -0700
  • 765b90f6a4 Stall on D$ lockups less conservatively Andrew Waterman 2016-05-21 16:56:49 -0700
  • a3061047e3 Instantiate blocking D$ when NMSHRS=0 Andrew Waterman 2016-05-21 16:56:17 -0700
  • 80482890fd Don't rely on tag value for nacks Andrew Waterman 2016-05-21 16:55:42 -0700
  • e19c5e5d2c IOMSHR: support atomic operations Wesley W. Terpstra 2016-05-16 18:28:45 -0700
  • a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts Wesley W. Terpstra 2016-05-12 12:18:47 -0700
  • ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) Wesley W. Terpstra 2016-05-12 18:51:02 -0700
  • b921bae107 ahb: eliminate trait abused for constants Wesley W. Terpstra 2016-05-24 14:14:57 -0700
  • 200c69c106 ahb: support hmastlock acquistion of crossbar Wesley W. Terpstra 2016-05-24 13:28:06 -0700
  • e1e8eda419 ahb: add a test SRAM Wesley W. Terpstra 2016-05-24 14:06:57 -0700
  • 1db40687c6 ahb: eliminate now-unnecesary non-standard hreadyin Wesley W. Terpstra 2016-05-18 16:46:28 -0700
  • 15cad8414d ahb: put signals in the order they appear in signal traces in the spec Wesley W. Terpstra 2016-05-18 16:45:15 -0700
  • f30f8d9f79 ahb: reduce obsolete degenerate cases of a crossbar Wesley W. Terpstra 2016-05-18 16:31:06 -0700
  • 0368b6db6b ahb: replace defective crossbar with a functional one Wesley W. Terpstra 2016-05-18 13:21:12 -0700
  • 2b37f37335 ahb: helper methods Wesley W. Terpstra 2016-05-18 16:23:32 -0700
  • ef2aae26a8 ahb: rename hreadyout to standard hready, mark hreadyin for death Wesley W. Terpstra 2016-05-18 15:59:54 -0700
  • 2f8a77f27a ahb: include all AHB-lite constants Wesley W. Terpstra 2016-05-18 15:57:10 -0700
  • 7896c4157e ahb: parameterize poci Wesley W. Terpstra 2016-05-18 16:10:57 -0700
  • 93447eb274 ahb: make hasti parameters location sensitive Wesley W. Terpstra 2016-05-24 14:06:03 -0700
  • 00d31dc5c5 bram: use new hasti definitions Wesley W. Terpstra 2016-05-24 13:26:26 -0700
  • ee0acc1d07 Fix BRAM assertion condition Albert Ou 2016-05-23 13:19:53 -0700
  • 05c0808ff2 Update trace generation and checking scripts Matthew Naylor 2016-05-23 17:02:15 +0100