riscv/rocket-chip
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Fix arithmetic in ROM row count

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This commit is contained in:
Andrew Waterman 2016-06-01 21:56:24 -07:00
parent 8e80d1ec80
commit 9518b3d589
2 changed files with 3 additions and 3 deletions
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2
uncore/src/main/scala/debug.scala
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@ -802,7 +802,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
// Inspired by ROMSlave
val romContents = cfg.debugRomContents.get
val romByteWidth = tlDataBits / 8
val romRows = Math.ceil((romContents.size + romByteWidth)/romByteWidth).toInt
val romRows = (romContents.size + romByteWidth - 1)/romByteWidth
val romMem = Vec.tabulate(romRows) { ii =>
val slice = romContents.slice(ii*romByteWidth, (ii+1)*romByteWidth)
UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8)

4
uncore/src/main/scala/rom.scala
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@ -19,7 +19,7 @@ class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
when (io.acquire.fire()) { addr_beat := io.acquire.bits.addr_beat }
val byteWidth = tlDataBits / 8
val rows = (contents.size + byteWidth - 1)/byteWidth + 1
val rows = (contents.size + byteWidth - 1)/byteWidth
val rom = Vec.tabulate(rows) { i =>
val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
@ -52,7 +52,7 @@ class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
io.b.valid := Bool(false)
val byteWidth = io.r.bits.nastiXDataBits / 8
val rows = (contents.size + byteWidth - 1)/byteWidth + 1
val rows = (contents.size + byteWidth - 1)/byteWidth
val rom = Vec.tabulate(rows) { i =>
val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)