riscv/rocket-chip
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bump chisel

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This commit is contained in:
Andrew Waterman
2016-05-25 11:09:37 -07:00
parent f52fc655a5
commit a8462d3cfc
5 changed files with 8 additions and 6 deletions
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3
Makefrag
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@ -9,8 +9,7 @@ CXX ?= g++
CXXFLAGS := -O1
CHISEL_VERSION ?= 2
CHISEL_SUBMODULE ?= chisel$(CHISEL_VERSION)
export CHISEL_SUBMODULE
export CHISEL_VERSION
SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar
SHELL := /bin/bash

2
chisel2

Submodule chisel2 updated: c736c900ae...e9e5bb28ac

2
chisel3

Submodule chisel3 updated: 3ae577bc71...d742d70a05

2
firrtl

Submodule firrtl updated: a73efa2f67...26694d3496

5
project/build.scala
View File

@ -15,7 +15,10 @@ object BuildSettings extends Build {
libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)
)
lazy val chisel = project in file(sys.env.getOrElse("CHISEL_SUBMODULE", "chisel2"))
lazy val chiselMacros = project in file("chisel3/chiselMacros")
lazy val chiselFrontend = project in file("chisel3/chiselFrontend")
lazy val chisel = project in file("chisel" + sys.env.getOrElse("CHISEL_VERSION", 2)) dependsOn(chiselMacros, chiselFrontend)
lazy val cde = project in file("context-dependent-environments")
lazy val hardfloat = project.dependsOn(chisel)
lazy val junctions = project.dependsOn(chisel, cde)