Cope with changes to AddrMap
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@ -185,7 +185,7 @@ class TraceGenerator(id: Int)
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// Address bag, shared by all cores, taken from module parameters.
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// In addition, there is a per-core random selection of extra addresses.
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val addrHashMap = p(GlobalAddrHashMap)
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val addrHashMap = p(GlobalAddrMap)
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val baseAddr = addrHashMap("mem").start + 0x01000000
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val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))
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