riscv/rocket-chip
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Update trace generation and checking scripts

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Pass the elf file (that specifies the tohost and fromhost addresses)
to the emulator in the trace generator & checker scripts.
This commit is contained in:
Matthew Naylor 2016-05-23 17:02:15 +01:00
parent 87be2bcd60
commit 05c0808ff2
3 changed files with 16 additions and 7 deletions
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9
groundtest/scripts/tracegen+check.sh
View File

@ -37,6 +37,7 @@ AXE=${AXE-axe}
MODEL=${MODEL-WMO}
LOG_DIR=${LOG_DIR-tracegen-log}
TRACE_STATS=${TRACE_STATS-tracestats.py}
ELF_FILE=${ELF_FILE-../riscv-tools/riscv-tests/build/isa/rv64ui-p-simple}
###############################################################################
@ -75,6 +76,12 @@ if [ ! `command -v $TRACE_STATS` ]; then
exit -1
fi
if [ ! -f $ELF_FILE ]; then
echo Can\'t find dummy elf file for ground tests
echo Please run build.sh in riscv-tools to produce \'rv64ui-p-simple\'
exit -1
fi
if [ "$MODEL" != SC -a \
"$MODEL" != TSO -a \
"$MODEL" != PSO -a \
@ -112,7 +119,7 @@ for (( I = $START_SEED; I <= $END_SEED; I++ )); do
fi
# Generate trace
$TRACE_GEN $EMU $I > $LOG/trace.txt
$TRACE_GEN $EMU $I $ELF_FILE > $LOG/trace.txt
if [ ! $? -eq 0 ]; then
echo -e "\n\nError: emulator returned non-zero exit code"
echo See $LOG/trace.txt for details

7
groundtest/scripts/tracegen.py
View File

@ -33,11 +33,12 @@ import subprocess
import re
def main():
if len(sys.argv) != 3:
sys.stderr.write("Usage: tracegen.py EMULATOR SEED\n")
if len(sys.argv) != 4:
sys.stderr.write("Usage: tracegen.py EMULATOR SEED ELF\n")
sys.exit(-1)
p = subprocess.Popen([sys.argv[1], "+verbose", "-s" + sys.argv[2]],
p = subprocess.Popen([sys.argv[1],
"+verbose", "-s" + sys.argv[2], sys.argv[3]],
stderr=subprocess.PIPE, stdout=subprocess.PIPE)
if p == None:
sys.stderr.write("File not found: " + sys.argv[1] + "\n")

7
groundtest/src/main/scala/tracegen.scala
View File

@ -186,8 +186,9 @@ class TraceGenerator(id: Int)
// In addition, there is a per-core random selection of extra addresses.
val addrHashMap = p(GlobalAddrHashMap)
val memStart = addrHashMap("mem").start
val bagOfAddrs = addressBag.map(x => UInt(memStart + x, numBitsInWord))
val baseAddr = addrHashMap("mem").start + 0x01000000
val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))
val extraAddrs = (0 to numExtraAddrs-1).
map(i => Reg(UInt(width = 16)))
@ -467,7 +468,7 @@ class TraceGenerator(id: Int)
// Wire up interface to memory
io.mem.req.valid := reqValid
io.mem.req.bits.addr := reqAddr
io.mem.req.bits.addr := reqAddr + UInt(baseAddr)
io.mem.req.bits.data := reqData
io.mem.req.bits.typ := MT_D
io.mem.req.bits.cmd := reqCmd