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Work around another zero-width wire limitation

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This commit is contained in:
Andrew Waterman 2016-05-25 21:42:02 -07:00
parent e2755a0f0a
commit 22568de5f3
1 changed files with 4 additions and 5 deletions
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9
uncore/src/main/scala/tilelink.scala
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@ -170,16 +170,15 @@ trait HasAcquireUnion extends HasTileLinkParameters {
def op_size(dummy: Int = 0) = union(addrByteOff-1, opSizeOff)
/** Byte address for [[uncore.PutAtomic]] operand */
def addr_byte(dummy: Int = 0) = union(addrByteMSB-1, addrByteOff)
def amo_offset(dummy: Int = 0) = addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBytes))
def amo_offset(dummy: Int = 0) =
if (tlByteAddrBits > log2Up(amoAluOperandBytes)) addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBytes))
else UInt(0)
/** Bit offset of [[uncore.PutAtomic]] operand */
def amo_shift_bytes(dummy: Int = 0) = UInt(amoAluOperandBytes)*amo_offset()
/** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */
def wmask(dummy: Int = 0): UInt = {
val amo_word_mask =
if (amoAluOperandBytes == tlWriteMaskBits) UInt(1)
else UIntToOH(amo_offset())
Mux(isBuiltInType(Acquire.putAtomicType),
FillInterleaved(amoAluOperandBytes, amo_word_mask),
FillInterleaved(amoAluOperandBytes, UIntToOH(amo_offset())),
Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
union(tlWriteMaskBits, 1),
UInt(0, width = tlWriteMaskBits)))