riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Instantiate blocking D$ when NMSHRS=0

Browse Source
This commit is contained in:
Andrew Waterman
2016-05-21 16:56:17 -07:00
parent 80482890fd
commit a3061047e3
1 changed files with 6 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
rocket/src/main/scala/tile.scala
View File

@@ -40,13 +40,15 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val icache = Module(new Frontend()(p.alterPartial({
case CacheName => "L1I"
case CoreName => "Rocket" })))
val dcache = Module(new HellaCache()(dcacheParams))
val dcache =
if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
else Module(new HellaCache()(dcacheParams)).io
val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.io.ptw)
val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.ptw)
val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem)
core.io.prci <> io.prci
icache.io.cpu <> core.io.imem
@@ -133,7 +135,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
dcArb.io.requestor <> dcPorts
dcache.io.cpu <> dcArb.io.mem
dcache.cpu <> dcArb.io.mem
if (!usingRocc || nFPUPorts == 0) {
fpuOpt.foreach { fpu =>