Instantiate blocking D$ when NMSHRS=0
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@ -40,13 +40,15 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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val icache = Module(new Frontend()(p.alterPartial({
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case CacheName => "L1I"
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case CoreName => "Rocket" })))
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcache =
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if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
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else Module(new HellaCache()(dcacheParams)).io
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val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.io.ptw)
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val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.ptw)
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val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
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val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
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val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
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val cachedPorts = collection.mutable.ArrayBuffer(dcache.io.mem)
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val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem)
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core.io.prci <> io.prci
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icache.io.cpu <> core.io.imem
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@ -133,7 +135,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
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val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
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dcArb.io.requestor <> dcPorts
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dcache.io.cpu <> dcArb.io.mem
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dcache.cpu <> dcArb.io.mem
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if (!usingRocc || nFPUPorts == 0) {
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fpuOpt.foreach { fpu =>
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