riscv/rocket-chip
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Can't assign to Vec literals

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This commit is contained in:
Andrew Waterman 2016-06-01 23:36:34 -07:00
parent 20e1de08da
commit 0866b4c045
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/debug.scala
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@ -593,7 +593,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
sbRamWrData := sbWrData
require (dbRamAddrWidth >= ramAddrWidth) // SB accesses less than 32 bits Not Implemented.
val dbRamWrMask = Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))}
val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
if (dbRamDataWidth < ramDataWidth){