riscv/rocket-chip
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This commit is contained in:
Andrew Waterman 2016-05-25 11:08:11 -07:00
parent a8462d3cfc
commit e82c080c3c
10 changed files with 70 additions and 63 deletions
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63
README.md
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@ -287,20 +287,20 @@ Now take a look in the emulator/generated-src directory. You will find
Chisel generated C++ code.
$ ls $ROCKETCHIP/emulator/generated-src
Top.DefaultCPPConfig-0.cpp
Top.DefaultCPPConfig-0.o
Top.DefaultCPPConfig-1.cpp
Top.DefaultCPPConfig-1.o
Top.DefaultCPPConfig-2.cpp
Top.DefaultCPPConfig-2.o
Top.DefaultCPPConfig-3.cpp
Top.DefaultCPPConfig-3.o
Top.DefaultCPPConfig-4.cpp
Top.DefaultCPPConfig-4.o
Top.DefaultCPPConfig-5.cpp
Top.DefaultCPPConfig-5.o
Top.DefaultCPPConfig.cpp
Top.DefaultCPPConfig.h
Top.DefaultConfig-0.cpp
Top.DefaultConfig-0.o
Top.DefaultConfig-1.cpp
Top.DefaultConfig-1.o
Top.DefaultConfig-2.cpp
Top.DefaultConfig-2.o
Top.DefaultConfig-3.cpp
Top.DefaultConfig-3.o
Top.DefaultConfig-4.cpp
Top.DefaultConfig-4.o
Top.DefaultConfig-5.cpp
Top.DefaultConfig-5.o
Top.DefaultConfig.cpp
Top.DefaultConfig.h
emulator.h
emulator_api.h
emulator_mod.h
@ -366,13 +366,13 @@ You can generate Verilog for your VLSI flow with the following commands:
$ make verilog
Now take a look at vsim/generated-src, and the contents of the
Top.DefaultVLSIConfig.conf file:
Top.DefaultConfig.conf file:
$ cd $ROCKETCHIP/vsim/generated-src
Top.DefaultVLSIConfig.conf
Top.DefaultVLSIConfig.prm
Top.DefaultVLSIConfig.v
consts.DefaultVLSIConfig.vh
Top.DefaultConfig.conf
Top.DefaultConfig.prm
Top.DefaultConfig.v
consts.DefaultConfig.vh
$ cat $ROCKETCHIP/vsim/generated-src/*.conf
name MetadataArray_tag_arr depth 128 width 84 ports mwrite,read mask_gran 21
name ICache_tag_array depth 128 width 38 ports mrw mask_gran 19
@ -387,7 +387,7 @@ script with the generated configuration file as an argument, which will
fill in the Verilog for the SRAMs. Currently, the $(mem\_gen) script
points to vsim/vlsi\_mem\_gen, which simply instantiates behavioral
SRAMs. You will see those SRAMs being appended at the end of
vsim/generated-src/Top.DefaultVLSIConfig.v. To target vendor-specific
vsim/generated-src/Top.DefaultConfig.v. To target vendor-specific
SRAMs, you will need to make necessary changes to vsim/vlsi\_mem\_gen.
Similarly, if you have access to VCS, you can run assembly tests and
@ -403,20 +403,17 @@ tests and benchmarks.
## <a name="param"></a> How can I parameterize my Rocket chip?
By now, you probably figured out that all generated files have a
configuration name attached, e.g. DefaultCPPConfig and
DefaultVLSIConfig. Take a look at src/main/scala/Configs.scala.
Search for NSets and NWays defined in DefaultConfig. You can change
those numbers to get a Rocket core with different cache parameters. For
example, by changing L1I, NWays to 4, you will get a 32KB 4-way
set-associative L1 instruction cache rather than a 16KB 2-way
set-associative L1 instruction cache. By searching further for
DefaultVLSIConfig and DefaultCPPConfig, you will see that currently both
are set to be identical to DefaultConfig.
By now, you probably figured out that all generated files have a configuration
name attached, e.g. DefaultConfig. Take a look at
src/main/scala/Configs.scala. Search for NSets and NWays defined in
BaseConfig. You can change those numbers to get a Rocket core with different
cache parameters. For example, by changing L1I, NWays to 4, you will get
a 32KB 4-way set-associative L1 instruction cache rather than a 16KB 2-way
set-associative L1 instruction cache.
Further down, you will be able to see two FPGA configurations:
DefaultFPGAConfig and DefaultFPGASmallConfig. DefaultFPGAConfig inherits from
DefaultConfig, but overrides the low-performance memory port (i.e., backup
BaseConfig, but overrides the low-performance memory port (i.e., backup
memory port) to be turned off. This is because the high-performance memory
port is directly connected to the high-performance AXI interface on the ZYNQ
FPGA. DefaultFPGASmallConfig inherits from DefaultFPGAConfig, but changes the
@ -426,12 +423,12 @@ This small configuration is used for the Zybo FPGA board, which has the
smallest ZYNQ part.
Towards the end, you can also find that ExampleSmallConfig inherits all
parameters from DefaultConfig but overrides the same parameters of
parameters from BaseConfig but overrides the same parameters of
SmallConfig.
Now take a look at fsim/Makefile and vsim/Makefile. Search for the
CONFIG variable. DefaultFPGAConfig is used for the FPGA build, while
DefaultVLSIConfig is used for the VLSI build. You can also change the
DefaultConfig is used for the VLSI build. You can also change the
CONFIG variable on the make command line:
$ cd $ROCKETCHIP/vsim

2
emulator/Makefile
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@ -7,7 +7,7 @@ sim_dir = .
output_dir = $(sim_dir)/output
BACKEND = c
CONFIG ?= DefaultCPPConfig
CONFIG ?= DefaultConfig
include $(base_dir)/Makefrag

2
junctions

@ -1 +1 @@
Subproject commit 7aaaa59d96f998d38d0969894cf9ec0e1fcfed22
Subproject commit c02574d2fa6710978642bce85dfda95505eb8c8a

2
riscv-tools

@ -1 +1 @@
Subproject commit b9b3f491ba8987bb94e3a85dcc0c8d80716d8d41
Subproject commit ffd20b64afa18acdc60bc799346477d96236f21d

2
rocket

@ -1 +1 @@
Subproject commit ffbbb85829d6e9d36aee871d8af2891c1c0ba99e
Subproject commit 8df0593d0ed0c2e58f3687c37ac03784fcad075f

50
src/main/scala/Configs.scala
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@ -19,7 +19,7 @@ object ConfigUtils {
}
import ConfigUtils._
class DefaultConfig extends Config (
class BaseConfig extends Config (
topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
@ -78,7 +78,7 @@ class DefaultConfig extends Config (
res append "};\n"
res append "core {\n"
for (i <- 0 until site(NTiles)) {
val isa = s"rv${site(XLen)}ima${if (site(UseFPU)) "fd" else ""}"
val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
val prciAddr = addrMap(s"io:int:prci$i").start
res append s" $i {\n"
@ -215,6 +215,11 @@ class DefaultConfig extends Config (
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
true
}
case UseAtomics => {
val env = if(site(UseVM)) List("p","v") else List("p")
TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
true
}
case NExtInterrupts => 2
case NExtMMIOChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
@ -304,8 +309,7 @@ class DefaultConfig extends Config (
case _ => throw new CDEMatchError
}
)
class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig
class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
class With2Cores extends Config(knobValues = { case "NTILES" => 2; case _ => throw new CDEMatchError })
class With4Cores extends Config(knobValues = { case "NTILES" => 4; case _ => throw new CDEMatchError })
@ -379,9 +383,7 @@ class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1; case _ => t
class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2; case _ => throw new CDEMatchError })
class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4; case _ => throw new CDEMatchError })
class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig)
class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig)
class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
@ -390,6 +392,7 @@ class WithRV32 extends Config(
(pname,site,here) => pname match {
case XLen => 32
case UseVM => false
case UseAtomics => false
case UseFPU => false
case _ => throw new CDEMatchError
}
@ -403,7 +406,14 @@ class FPGAConfig extends Config (
}
)
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new DefaultConfig)
class WithBlockingL1 extends Config (
knobValues = {
case "L1D_MSHRS" => 0
case _ => throw new CDEMatchError
}
)
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
class SmallConfig extends Config (
topDefinitions = { (pname,site,here) => pname match {
@ -421,30 +431,30 @@ class SmallConfig extends Config (
case "L1D_WAYS" => 1
case "L1I_SETS" => 64
case "L1I_WAYS" => 1
case "L1D_MSHRS" => 1
case "L1D_MSHRS" => 0
case _ => throw new CDEMatchError
}
)
class DefaultFPGASmallConfig extends Config(new SmallConfig ++ new DefaultFPGAConfig)
class DefaultRV32Config extends Config(new SmallConfig ++ new WithRV32 ++ new DefaultConfig)
class DefaultRV32Config extends Config(new SmallConfig ++ new WithRV32 ++ new BaseConfig)
class ExampleSmallConfig extends Config(new SmallConfig ++ new DefaultConfig)
class ExampleSmallConfig extends Config(new SmallConfig ++ new BaseConfig)
class DualBankConfig extends Config(new With2BanksPerMemChannel ++ new DefaultConfig)
class DualBankConfig extends Config(new With2BanksPerMemChannel ++ new BaseConfig)
class DualBankL2Config extends Config(
new With2BanksPerMemChannel ++ new WithL2Cache ++ new DefaultConfig)
new With2BanksPerMemChannel ++ new WithL2Cache ++ new BaseConfig)
class DualChannelConfig extends Config(new With2MemoryChannels ++ new DefaultConfig)
class DualChannelConfig extends Config(new With2MemoryChannels ++ new BaseConfig)
class DualChannelL2Config extends Config(
new With2MemoryChannels ++ new WithL2Cache ++ new DefaultConfig)
new With2MemoryChannels ++ new WithL2Cache ++ new BaseConfig)
class DualChannelDualBankConfig extends Config(
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new DefaultConfig)
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new BaseConfig)
class DualChannelDualBankL2Config extends Config(
new With2MemoryChannels ++ new With2BanksPerMemChannel ++
new WithL2Cache ++ new DefaultConfig)
new WithL2Cache ++ new BaseConfig)
class WithRoccExample extends Config(
(pname, site, here) => pname match {
@ -464,7 +474,7 @@ class WithRoccExample extends Config(
case _ => throw new CDEMatchError
})
class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
class WithDmaController extends Config(
(pname, site, here) => pname match {
@ -500,9 +510,9 @@ class DualChannelBenchmarkConfig extends Config(new With2MemoryChannels ++ new S
class QuadChannelBenchmarkConfig extends Config(new With4MemoryChannels ++ new SingleChannelBenchmarkConfig)
class OctoChannelBenchmarkConfig extends Config(new With8MemoryChannels ++ new SingleChannelBenchmarkConfig)
class EightChannelVLSIConfig extends Config(new With8MemoryChannels ++ new DefaultVLSIConfig)
class EightChannelConfig extends Config(new With8MemoryChannels ++ new BaseConfig)
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
class DualCoreConfig extends Config(new With2Cores ++ new DefaultConfig)
class DualCoreConfig extends Config(new With2Cores ++ new BaseConfig)

2
src/main/scala/TestConfigs.scala
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@ -141,7 +141,7 @@ class WithTraceGen extends Config(
case _ => throw new CDEMatchError
})
class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)

6
src/main/scala/Testing.scala
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@ -103,7 +103,7 @@ object DefaultTestSuites {
val rv32umNames = LinkedHashSet("mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu")
val rv32um = new AssemblyTestSuite("rv32um", "rv32ui", rv32umNames)(_)
val rv32uaNames = LinkedHashSet("amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
val rv32ua = new AssemblyTestSuite("rv32ua", "rv32ui", rv32uaNames)(_)
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
@ -112,7 +112,7 @@ object DefaultTestSuites {
val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um, rv32ua)
val rv32u = List(rv32ui, rv32um)
val rv32i = List(rv32ui, rv32si, rv32mi)
val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw")
@ -140,7 +140,7 @@ object DefaultTestSuites {
// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
val rv64u = List(rv64ui, rv64um, rv64ua)
val rv64u = List(rv64ui, rv64um)
val rv64i = List(rv64ui, rv64si, rv64mi)
val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(

2
uncore

@ -1 +1 @@
Subproject commit cf7534a5369e8af03e8d793c6b32f36916c1a13b
Subproject commit 2b1da9213aa43cb37d3e7da7d9146825856ec6ef

2
vsim/Makefile
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@ -16,7 +16,7 @@ sim_dir = .
output_dir = $(sim_dir)/output
BACKEND ?= v
CONFIG ?= DefaultVLSIConfig
CONFIG ?= DefaultConfig
TB ?= rocketTestHarness
include $(base_dir)/Makefrag