ahb: TileLink => AHB bridge, including atomics and bursts
This commit is contained in:
Wesley W. Terpstra
parent
ace9362d81
commit
a012341d96
403
uncore/src/main/scala/ahb.scala
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403
uncore/src/main/scala/ahb.scala
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package uncore
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import Chisel._
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import junctions._
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import cde.{Parameters, Field}
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import HastiConstants._
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/* We need to translate TileLink requests into operations we can actually execute on AHB.
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* The general plan of attack is:
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* get => one AHB=>TL read
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* put => [multiple AHB write fragments=>nill], one AHB write=>TL
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* getBlock => AHB burst reads =>TL
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* putBlock => AHB burst writes=>TL
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* getPrefetch => noop=>TL
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* putPrefetch => noop=>TL
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* putAtomic => one AHB=>TL read, one idle, one AHB atom_write=>nill, one idle
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*
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* This requires that we support a pipeline of optional AHB requests with optional TL responses
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*/
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class AHBRequestIO(implicit p: Parameters) extends HastiMasterIO
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with HasGrantType
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with HasClientTransactionId
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with HasTileLinkBeatId {
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val executeAHB = Bool()
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val respondTL = Bool()
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val latchAtom = Bool()
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val firstBurst = Bool()
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val finalBurst = Bool()
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val cmd = Bits(width = M_SZ) // atomic op
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}
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// AHB stage1: translate TileLink Acquires into AHBRequests
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class AHBTileLinkIn(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val acquire = new DecoupledIO(new Acquire).flip // NOTE: acquire must be either a Queue or a Pipe
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val request = new DecoupledIO(new AHBRequestIO)
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}
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// Match the AHB burst with a TileLink {Put,Get}Block
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val burstSize = tlDataBeats match {
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case 1 => HBURST_SINGLE
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// case 2 not supported by AHB
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case 4 => HBURST_WRAP4
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case 8 => HBURST_WRAP8
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case 16 => HBURST_WRAP16
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case _ => throw new java.lang.AssertionError("TileLink beats unsupported by AHB")
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}
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// Bursts start at 0 and wrap-around back to 0
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val finalBurst = SInt(-1, width = log2Up(tlDataBeats)).asUInt
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val firstBurst = UInt(0, width = log2Up(tlDataBeats))
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val next_wmask = Wire(UInt(width = tlDataBytes)) // calculated below
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// State variables for processing more complicated TileLink Acquires
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val s_atom_r :: s_atom_idle1 :: s_atom_w :: s_atom_idle2 :: Nil = Enum(UInt(), 4)
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val atom_state = Reg(init = s_atom_r)
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val done_wmask = Reg(init = UInt(0, width = tlDataBytes))
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val burst = Reg(init = firstBurst)
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// Grab some view of the TileLink acquire
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val acq_wmask = io.acquire.bits.wmask()
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val isReadBurst = io.acquire.bits.is(Acquire.getBlockType)
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val isWriteBurst = io.acquire.bits.is(Acquire.putBlockType)
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val isBurst = isWriteBurst || isReadBurst
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val isAtomic = io.acquire.bits.is(Acquire.putAtomicType)
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val isPut = io.acquire.bits.is(Acquire.putType)
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// Final states?
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val last_wmask = next_wmask === acq_wmask
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val last_atom = atom_state === s_atom_idle2
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val last_burst = burst === finalBurst
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// Block the incoming request until we've fully consumed it
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// NOTE: the outgoing grant.valid may happen while acquire.ready is still false;
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// for this reason it is essential to have a Queue or a Pipe infront of acquire
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io.acquire.ready := io.request.ready && MuxLookup(io.acquire.bits.a_type, Bool(true), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> last_burst, // hold it until the last beat is burst
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Acquire.putType -> last_wmask, // only accept the put if we can fully consume its wmask
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> last_atom, // atomic operation stages complete
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Acquire.getPrefetchType -> Bool(true),
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Acquire.putPrefetchType -> Bool(true)))
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// Advance the fragment state
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when (io.request.ready && io.acquire.valid && isPut) {
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when (last_wmask) { // if this was the last fragment, restart FSM
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done_wmask := UInt(0)
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} .otherwise {
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done_wmask := next_wmask
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}
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}
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// Advance the burst state
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// We assume here that TileLink gives us all putBlock beats with nothing between them
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when (io.request.ready && io.acquire.valid && isBurst) {
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burst := burst + UInt(1) // overflow => wraps around to 0
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}
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// Advance the atomic state machine
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when (io.request.ready && io.acquire.valid && isAtomic) {
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switch (atom_state) {
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is (s_atom_r) { atom_state := s_atom_idle1 }
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is (s_atom_idle1) { atom_state := s_atom_w } // idle1 => AMOALU runs on a different clock than AHB slave read
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is (s_atom_w) { atom_state := s_atom_idle2 }
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is (s_atom_idle2) { atom_state := s_atom_r } // idle2 state is required by AHB after hmastlock is lowered
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}
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}
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// Returns (range=0, range=-1, aligned_wmask, size)
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def mask_helper(in_0 : Bool, range : UInt): (Bool, Bool, UInt, UInt) = {
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val len = range.getWidth
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if (len == 1) {
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(range === UInt(0), range === UInt(1), in_0.asUInt() & range, UInt(0))
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} else {
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val mid = len / 2
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val lo = range(mid-1, 0)
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val hi = range(len-1, mid)
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val (lo_0, lo_1, lo_m, lo_s) = mask_helper(in_0, lo)
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val (hi_0, hi_1, hi_m, hi_s) = mask_helper(in_0 && lo_0, hi)
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val out_0 = lo_0 && hi_0
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val out_1 = lo_1 && hi_1
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val out_m = Cat(hi_m, lo_m) | Fill(len, (in_0 && out_1).asUInt())
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val out_s = Mux(out_1, UInt(log2Up(len)), Mux(lo_0, hi_s, lo_s))
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(out_0, out_1, out_m, out_s)
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}
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}
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val pending_wmask = acq_wmask & ~done_wmask
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val put_addr = PriorityEncoder(pending_wmask)
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val (wmask_0, _, exec_wmask, put_size) = mask_helper(Bool(true), pending_wmask)
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next_wmask := done_wmask | exec_wmask
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// Calculate the address, with consideration to put fragments and bursts
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val addr_block = io.acquire.bits.addr_block
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val addr_beat = io.acquire.bits.addr_beat
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val addr_burst = Mux(isReadBurst, addr_beat + burst, addr_beat)
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val addr_byte = Mux(isPut, put_addr, io.acquire.bits.addr_byte())
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val ahbAddr = Cat(addr_block, addr_burst, addr_byte)
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val ahbSize = Mux(isPut, put_size, Mux(isBurst, UInt(log2Up(tlDataBytes)), io.acquire.bits.op_size()))
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val ahbBurst = MuxLookup(io.acquire.bits.a_type, HBURST_SINGLE, Array(
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Acquire.getType -> HBURST_SINGLE,
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Acquire.getBlockType -> burstSize,
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Acquire.putType -> HBURST_SINGLE,
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Acquire.putBlockType -> burstSize,
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Acquire.putAtomicType -> HBURST_SINGLE,
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Acquire.getPrefetchType -> HBURST_SINGLE,
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Acquire.putPrefetchType -> HBURST_SINGLE))
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val ahbWrite = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(false),
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Acquire.getBlockType -> Bool(false),
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Acquire.putType -> Bool(true),
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(false),
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s_atom_idle1 -> Bool(false), // don't care
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s_atom_w -> Bool(true),
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s_atom_idle2 -> Bool(true))), // don't care
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Acquire.getPrefetchType -> Bool(false), // don't care
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Acquire.putPrefetchType -> Bool(true))) // don't care
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val ahbExecute = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> Bool(true),
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Acquire.putType -> !wmask_0, // handle the case of a Put with no bytes!
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(true),
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s_atom_idle1 -> Bool(false),
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s_atom_w -> Bool(true),
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s_atom_idle2 -> Bool(false))),
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Acquire.getPrefetchType -> Bool(false),
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Acquire.putPrefetchType -> Bool(false)))
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val respondTL = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> Bool(true),
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Acquire.putType -> last_wmask,
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(true), // they want the old data
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s_atom_idle1 -> Bool(false),
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s_atom_w -> Bool(false),
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s_atom_idle2 -> Bool(false))),
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Acquire.getPrefetchType -> Bool(true),
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Acquire.putPrefetchType -> Bool(true)))
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io.request.valid := io.acquire.valid
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io.request.bits.htrans := HTRANS_IDLE // unused/ignored
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io.request.bits.haddr := ahbAddr
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io.request.bits.hmastlock := isAtomic && atom_state =/= s_atom_idle2
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io.request.bits.hwrite := ahbWrite
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io.request.bits.hburst := ahbBurst
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io.request.bits.hsize := ahbSize
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io.request.bits.hprot := HPROT_DATA | HPROT_PRIVILEGED
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io.request.bits.hwdata := io.acquire.bits.data
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io.request.bits.executeAHB := ahbExecute
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io.request.bits.respondTL := respondTL
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io.request.bits.latchAtom := isAtomic && atom_state === s_atom_r
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io.request.bits.firstBurst := burst === firstBurst
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io.request.bits.finalBurst := burst === finalBurst || !isBurst
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io.request.bits.cmd := io.acquire.bits.op_code()
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io.request.bits.is_builtin_type := Bool(true)
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io.request.bits.g_type := io.acquire.bits.getBuiltInGrantType()
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io.request.bits.client_xact_id := io.acquire.bits.client_xact_id
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io.request.bits.addr_beat := addr_burst
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val debugBurst = Reg(UInt())
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debugBurst := addr_burst - burst
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// We only support built-in TileLink requests
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assert(!io.acquire.valid || io.acquire.bits.is_builtin_type, "AHB bridge only supports builtin TileLink types")
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// Ensure alignment of address to size
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assert(!io.acquire.valid || (ahbAddr & ((UInt(1) << ahbSize) - UInt(1))) === UInt(0), "TileLink operation misaligned")
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// If this is a putBlock, make sure it moves properly
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assert(!io.acquire.valid || !isBurst || burst === firstBurst || debugBurst === addr_burst - burst, "TileLink putBlock beats not sequential")
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// We better not get an incomplete TileLink acquire
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assert(!io.acquire.valid || isBurst || burst === firstBurst, "TileLink never completed a putBlock")
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}
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// AHB stage2: execute AHBRequests
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class AHBBusMaster(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val request = new DecoupledIO(new AHBRequestIO).flip
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val grant = new DecoupledIO(new Grant)
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val ahb = new HastiMasterIO()
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}
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// All AHB outputs are registered (they might be IOs)
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val midBurst = Reg(init = Bool(false))
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val htrans = Reg(init = HTRANS_IDLE)
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val haddr = Reg(UInt())
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val hmastlock = Reg(init = Bool(false))
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val hwrite = Reg(Bool())
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val hburst = Reg(UInt())
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val hsize = Reg(UInt())
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val hprot = Reg(UInt())
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val hwdata0 = Reg(Bits())
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val hwdata1 = Reg(Bits())
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val hrdata = Reg(Bits())
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io.ahb.htrans := htrans
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io.ahb.haddr := haddr
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io.ahb.hmastlock := hmastlock
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io.ahb.hwrite := hwrite
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io.ahb.hburst := hburst
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io.ahb.hsize := hsize
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io.ahb.hprot := hprot
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io.ahb.hwdata := hwdata1 // one cycle after the address phase
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// TileLink response data needed in data phase
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val respondTL0 = Reg(init = Bool(false))
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val respondTL1 = Reg(init = Bool(false))
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val latchAtom0 = Reg(init = Bool(false))
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val latchAtom1 = Reg(init = Bool(false))
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val bubble = Reg(init = Bool(true)) // nothing useful in address phase
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val cmd = Reg(Bits())
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val g_type0 = Reg(UInt())
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val g_type1 = Reg(UInt())
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val client_xact_id0 = Reg(Bits())
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val client_xact_id1 = Reg(Bits())
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val addr_beat0 = Reg(UInt())
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val addr_beat1 = Reg(UInt())
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val grant1 = Reg(new Grant)
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// It is allowed to progress from Idle/Busy during a wait state
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val addrReady = io.ahb.hready || bubble
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val dataReady = io.ahb.hready
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// Only accept a new AHBRequest if we have enough buffer space in the pad
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// to accomodate a persistent drop in TileLink's grant.ready
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io.request.ready := addrReady && io.grant.ready
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// htrans must be updated even if no request is valid
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when (addrReady) {
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when (io.request.fire() && io.request.bits.executeAHB) {
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midBurst := !io.request.bits.finalBurst
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when (io.request.bits.firstBurst) {
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htrans := HTRANS_NONSEQ
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} .otherwise {
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htrans := HTRANS_SEQ
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}
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} .otherwise {
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when (midBurst) {
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htrans := HTRANS_BUSY
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} .otherwise {
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htrans := HTRANS_IDLE
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}
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}
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}
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// Address phase, clear repondTL when we have nothing to do
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when (addrReady) {
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when (io.request.fire()) {
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respondTL0 := io.request.bits.respondTL
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latchAtom0 := io.request.bits.latchAtom
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bubble := Bool(false)
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} .otherwise {
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respondTL0 := Bool(false)
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latchAtom0 := Bool(false)
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bubble := Bool(true) // an atom-injected Idle is not a bubble!
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}
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}
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// Transfer bulk address phase
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when (io.request.fire()) {
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haddr := io.request.bits.haddr
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hmastlock := io.request.bits.hmastlock
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hwrite := io.request.bits.hwrite
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hburst := io.request.bits.hburst
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hsize := io.request.bits.hsize
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hprot := io.request.bits.hprot
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hwdata0 := io.request.bits.hwdata
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cmd := io.request.bits.cmd
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g_type0 := io.request.bits.g_type
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client_xact_id0 := io.request.bits.client_xact_id
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addr_beat0 := io.request.bits.addr_beat
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}
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// Execute Atomic ops
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val amo_p = p.alterPartial({
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case CacheBlockOffsetBits => hastiAddrBits
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case AmoAluOperandBits => hastiDataBits
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})
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val alu = Module(new AMOALU(rhsIsAligned = false)(amo_p))
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alu.io.addr := haddr
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alu.io.cmd := cmd
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alu.io.typ := hsize
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alu.io.rhs := hwdata0
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alu.io.lhs := hrdata
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// Transfer bulk data phase
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// NOTE: this introduces no bubbles because addrReady is a superset of dataReady
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when (dataReady) {
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hwdata1 := alu.io.out // hwdata1 := hwdata0
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respondTL1 := respondTL0
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latchAtom1 := latchAtom0
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g_type1 := g_type0
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client_xact_id1 := client_xact_id0
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addr_beat1 := addr_beat0
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}
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// Latch the read result for an atomic operation
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when (dataReady && latchAtom1) {
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hrdata := io.ahb.hrdata
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}
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// Only issue TL grant when the slave has provided data
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io.grant.valid := dataReady && respondTL1
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = g_type1,
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client_xact_id = client_xact_id1,
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manager_xact_id = UInt(0),
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addr_beat = addr_beat1,
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data = io.ahb.hrdata)
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// We cannot support errors from AHB to TileLink
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assert(!io.ahb.hresp, "AHB hresp error detected and cannot be reported via TileLink")
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}
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class AHBBridge(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val ahb = new HastiMasterIO()
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}
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// Hasti and TileLink widths must agree at this point in the topology
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require (tlDataBits == hastiDataBits)
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require (p(PAddrBits) == hastiAddrBits)
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// AHB does not permit bursts to cross a 1KB boundary
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require (tlDataBits * tlDataBeats <= 1024*8)
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// tlDataBytes must be a power of 2
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require (1 << log2Up(tlDataBytes) == tlDataBytes)
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// Create the sub-blocks
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val fsm = Module(new AHBTileLinkIn)
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val bus = Module(new AHBBusMaster)
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val pad = Module(new Queue(new Grant, 4))
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fsm.io.acquire <> Queue(io.tl.acquire, 2) // Pipe is also acceptable
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bus.io.request <> fsm.io.request
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io.ahb <> bus.io.ahb
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io.tl.grant <> pad.io.deq
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// The pad is needed to absorb AHB progress while !grant.ready
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// We are only 'ready' if the pad has at least 3 cycles of space
|
||||
bus.io.grant.ready := pad.io.count <= UInt(1)
|
||||
pad.io.enq.bits := bus.io.grant.bits
|
||||
pad.io.enq.valid := bus.io.grant.valid
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user