Merge AddrHashMap and AddrMap
This commit is contained in:
Andrew Waterman
parent
695be2f0ae
commit
28161cab45
@ -16,7 +16,6 @@ case object PPNBits extends Field[Int]
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case object VPNBits extends Field[Int]
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case object GlobalAddrMap extends Field[AddrMap]
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case object GlobalAddrHashMap extends Field[AddrHashMap]
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trait HasAddrMapParameters {
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implicit val p: Parameters
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@ -30,23 +29,27 @@ trait HasAddrMapParameters {
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val pgLevelBits = p(PgLevelBits)
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val asIdBits = p(ASIdBits)
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val addrMap = p(GlobalAddrHashMap)
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val addrMap = p(GlobalAddrMap)
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}
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case class MemAttr(prot: Int, cacheable: Boolean = false)
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abstract class MemRegion {
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def align: BigInt
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sealed abstract class MemRegion {
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def start: BigInt
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def size: BigInt
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def numSlaves: Int
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def attr: MemAttr
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def containsAddress(x: UInt) = UInt(start) <= x && x < UInt(start + size)
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}
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case class MemSize(size: BigInt, align: BigInt, attr: MemAttr) extends MemRegion {
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case class MemSize(size: BigInt, attr: MemAttr) extends MemRegion {
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def start = 0
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def numSlaves = 1
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}
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case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion {
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val numSlaves = entries.countSlaves
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val align = entries.computeAlign
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case class MemRange(start: BigInt, size: BigInt, attr: MemAttr) extends MemRegion {
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def numSlaves = 1
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}
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object AddrMapProt {
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@ -67,90 +70,80 @@ class AddrMapProt extends Bundle {
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case class AddrMapEntry(name: String, region: MemRegion)
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case class AddrHashMapEntry(port: Int, start: BigInt, region: MemRegion)
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class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
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private val hash = HashMap(entries.map(e => (e.name, e.region)):_*)
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def apply(index: Int): AddrMapEntry = entries(index)
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def length: Int = entries.size
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def countSlaves: Int = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
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def computeSize: BigInt = new AddrHashMap(this).size
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def computeAlign: BigInt = entries.map(_.region.align).foldLeft(BigInt(1))(_ max _)
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override def tail: AddrMap = new AddrMap(entries.tail)
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}
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object AddrMap {
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def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems)
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}
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class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) {
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private val mapping = HashMap[String, AddrHashMapEntry]()
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private val subMaps = HashMap[String, AddrHashMapEntry]()
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class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) extends MemRegion {
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def isEmpty = entries.isEmpty
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def length = entries.size
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def numSlaves = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
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def attr = ???
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private def genPairs(am: AddrMap, start: BigInt, startIdx: Int, prefix: String): (BigInt, Int) = {
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var ind = startIdx
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private val slavePorts = HashMap[String, Int]()
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private val mapping = HashMap[String, MemRegion]()
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val (size: BigInt, entries: Seq[AddrMapEntry]) = {
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var ind = 0
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var base = start
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am.foreach { ame =>
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val name = prefix + ame.name
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base = (base + ame.region.align - 1) / ame.region.align * ame.region.align
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ame.region match {
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case r: MemSize =>
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mapping += name -> AddrHashMapEntry(ind, base, r)
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base += r.size
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ind += 1
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case r: MemSubmap =>
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subMaps += name -> AddrHashMapEntry(-1, base, r)
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ind = genPairs(r.entries, base, ind, name + ":")._2
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base += r.size
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}}
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(base, ind)
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}
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var rebasedEntries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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for (AddrMapEntry(name, r) <- entriesIn) {
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if (r.start != 0) {
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val align = BigInt(1) << log2Ceil(r.size)
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require(r.start >= base, s"region $name base address 0x${r.start.toString(16)} overlaps previous base 0x${base.toString(16)}")
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require(r.start % align == 0, s"region $name base address 0x${r.start.toString(16)} not aligned to 0x${align.toString(16)}")
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base = r.start
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} else {
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base = (base + r.size - 1) / r.size * r.size
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}
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val size = genPairs(addrmap, start, 0, "")._1
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r match {
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case r: AddrMap =>
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val subMap = new AddrMap(r.entries, base)
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rebasedEntries += AddrMapEntry(name, subMap)
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mapping += name -> subMap
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mapping ++= subMap.mapping.map { case (k, v) => s"$name:$k" -> v }
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slavePorts ++= subMap.slavePorts.map { case (k, v) => s"$name:$k" -> (ind + v) }
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case _ =>
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val e = MemRange(base, r.size, r.attr)
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rebasedEntries += AddrMapEntry(name, e)
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mapping += name -> e
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slavePorts += name -> ind
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}
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val sortedEntries: Seq[(String, BigInt, MemSize)] = {
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val arr = new Array[(String, BigInt, MemSize)](mapping.size)
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mapping.foreach { case (name, AddrHashMapEntry(port, base, region)) =>
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arr(port) = (name, base, region.asInstanceOf[MemSize])
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ind += r.numSlaves
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base += r.size
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}
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arr.toSeq
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(base - start, rebasedEntries)
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}
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def nEntries: Int = mapping.size
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def apply(name: String): AddrHashMapEntry = mapping.getOrElse(name, subMaps(name))
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def subMap(name: String): (BigInt, AddrMap) = {
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val m = subMaps(name)
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(m.start, m.region.asInstanceOf[MemSubmap].entries)
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val flatten: Seq[(String, MemRange)] = {
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val arr = new Array[(String, MemRange)](slavePorts.size)
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for ((name, port) <- slavePorts)
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arr(port) = (name, mapping(name).asInstanceOf[MemRange])
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arr
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}
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def isInRegion(name: String, addr: UInt): Bool = {
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val start = mapping(name).start
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val size = mapping(name).region.size
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UInt(start) <= addr && addr < UInt(start + size)
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}
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def apply(name: String): MemRegion = mapping(name)
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def port(name: String): Int = slavePorts(name)
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def subMap(name: String): AddrMap = mapping(name).asInstanceOf[AddrMap]
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def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)
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def isCacheable(addr: UInt): Bool = {
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sortedEntries.filter(_._3.attr.cacheable).map { case (_, base, region) =>
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UInt(base) <= addr && addr < UInt(base + region.size)
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flatten.filter(_._2.attr.cacheable).map { case (_, region) =>
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region.containsAddress(addr)
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}.foldLeft(Bool(false))(_ || _)
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}
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def isValid(addr: UInt): Bool = {
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sortedEntries.map { case (_, base, region) =>
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addr >= UInt(base) && addr < UInt(base + region.size)
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flatten.map { case (_, region) =>
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region.containsAddress(addr)
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}.foldLeft(Bool(false))(_ || _)
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}
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def getProt(addr: UInt): AddrMapProt = {
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val protForRegion = sortedEntries.map { case (_, base, region) =>
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val inRegion = addr >= UInt(base) && addr < UInt(base + region.size)
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Mux(inRegion, UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
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val protForRegion = flatten.map { case (_, region) =>
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Mux(region.containsAddress(addr), UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
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}
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new AddrMapProt().fromBits(protForRegion.reduce(_|_))
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}
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@ -506,37 +506,29 @@ abstract class NastiInterconnect(implicit p: Parameters) extends NastiModule()(p
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lazy val io = new NastiInterconnectIO(nMasters, nSlaves)
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}
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class NastiRecursiveInterconnect(
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val nMasters: Int, val nSlaves: Int,
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addrmap: AddrMap, base: BigInt)
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class NastiRecursiveInterconnect(val nMasters: Int, addrMap: AddrMap)
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(implicit p: Parameters) extends NastiInterconnect()(p) {
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val levelSize = addrmap.size
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def port(name: String) = io.slaves(addrMap.port(name))
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val nSlaves = addrMap.numSlaves
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val routeSel = (addr: UInt) =>
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Cat(addrMap.entries.map(e => addrMap(e.name).containsAddress(addr)).reverse)
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val addrHashMap = new AddrHashMap(addrmap, base)
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val routeSel = (addr: UInt) => {
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Cat(addrmap.map { case entry =>
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val hashEntry = addrHashMap(entry.name)
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addr >= UInt(hashEntry.start) && addr < UInt(hashEntry.start + hashEntry.region.size)
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}.reverse)
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}
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val xbar = Module(new NastiCrossbar(nMasters, levelSize, routeSel))
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val xbar = Module(new NastiCrossbar(nMasters, addrMap.length, routeSel))
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xbar.io.masters <> io.masters
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io.slaves <> addrmap.zip(xbar.io.slaves).flatMap {
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io.slaves <> addrMap.entries.zip(xbar.io.slaves).flatMap {
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case (entry, xbarSlave) => {
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entry.region match {
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case _: MemSize =>
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Some(xbarSlave)
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case MemSubmap(_, submap) if submap.isEmpty =>
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case submap: AddrMap if submap.entries.isEmpty =>
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val err_slave = Module(new NastiErrorSlave)
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err_slave.io <> xbarSlave
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None
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case MemSubmap(_, submap) =>
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val subSlaves = submap.countSlaves
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val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, addrHashMap(entry.name).start))
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case submap: AddrMap =>
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val ic = Module(new NastiRecursiveInterconnect(1, submap))
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ic.io.masters.head <> xbarSlave
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ic.io.slaves
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case r: MemRange =>
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Some(xbarSlave)
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}
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}
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}
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