ahb: reduce obsolete degenerate cases of a crossbar
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@ -300,69 +300,9 @@ class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModul
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val slaves = Vec(amap.size, new HastiSlaveIO).flip
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}
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// skid buffer
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val skb_valid = Reg(init = Bool(false))
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val skb_haddr = Reg(UInt(width = hastiAddrBits))
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val skb_hwrite = Reg(Bool())
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val skb_hsize = Reg(UInt(width = SZ_HSIZE))
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val skb_hburst = Reg(UInt(width = SZ_HBURST))
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val skb_hprot = Reg(UInt(width = SZ_HPROT))
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val skb_htrans = Reg(UInt(width = SZ_HTRANS))
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val skb_hmastlock = Reg(Bool())
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val skb_hwdata = Reg(UInt(width = hastiDataBits))
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val master_haddr = Mux(skb_valid, skb_haddr, io.master.haddr)
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val master_hwrite = Mux(skb_valid, skb_hwrite, io.master.hwrite)
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val master_hsize = Mux(skb_valid, skb_hsize, io.master.hsize)
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val master_hburst = Mux(skb_valid, skb_hburst, io.master.hburst)
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val master_hprot = Mux(skb_valid, skb_hprot, io.master.hprot)
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val master_htrans = Mux(skb_valid, skb_htrans, io.master.htrans)
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val master_hmastlock = Mux(skb_valid, skb_hmastlock, io.master.hmastlock)
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val master_hwdata = Mux(skb_valid, skb_hwdata, io.master.hwdata)
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val hsels = PriorityEncoderOH(
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(io.slaves zip amap) map { case (s, afn) => {
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s.haddr := master_haddr
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s.hwrite := master_hwrite
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s.hsize := master_hsize
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s.hburst := master_hburst
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s.hprot := master_hprot
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s.htrans := master_htrans
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s.hmastlock := master_hmastlock
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s.hwdata := master_hwdata
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afn(master_haddr) && master_htrans.orR
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}})
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(io.slaves zip hsels) foreach { case (s, hsel) => {
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s.hsel := hsel
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s.hreadyin := skb_valid || io.master.hready
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} }
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val s1_hsels = Array.fill(amap.size){Reg(init = Bool(false))}
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val hreadys = io.slaves.map(_.hready)
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val master_hready = s1_hsels.reduce(_||_) === Bool(false) || Mux1H(s1_hsels, hreadys)
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when (master_hready) {
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val skid = s1_hsels.reduce(_||_) && (hsels zip hreadys).map{ case (s, r) => s && !r }.reduce(_||_)
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skb_valid := skid
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when (skid) {
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skb_haddr := io.master.haddr
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skb_hwrite := io.master.hwrite
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skb_hsize := io.master.hsize
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skb_hburst := io.master.hburst
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skb_hprot := io.master.hprot
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skb_htrans := io.master.htrans
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skb_hmastlock := io.master.hmastlock
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}
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(s1_hsels zip hsels) foreach { case (s1, s) =>
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s1 := s
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}
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}
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io.master.hready := !skb_valid && master_hready
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io.master.hrdata := Mux1H(s1_hsels, io.slaves.map(_.hrdata))
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io.master.hresp := Mux1H(s1_hsels, io.slaves.map(_.hresp))
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val bar = Module(new HastiXbar(1, amap))
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io.master <> bar.io.masters(0)
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io.slaves <> bar.io.slaves
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}
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class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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@ -370,68 +310,11 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val ins = Vec(n, new HastiSlaveIO)
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val out = new HastiSlaveIO().flip
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}
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// skid buffers
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val skb_valid = Array.fill(n){Reg(init = Bool(false))}
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val skb_haddr = Array.fill(n){Reg(UInt(width = hastiAddrBits))}
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val skb_hwrite = Array.fill(n){Reg(Bool())}
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val skb_hsize = Array.fill(n){Reg(UInt(width = SZ_HSIZE))}
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val skb_hburst = Array.fill(n){Reg(UInt(width = SZ_HBURST))}
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val skb_hprot = Array.fill(n){Reg(UInt(width = SZ_HPROT))}
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val skb_htrans = Array.fill(n){Reg(UInt(width = SZ_HTRANS))}
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val skb_hmastlock = Array.fill(n){Reg(Bool())}
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val requests = (io.ins zip skb_valid) map { case (in, v) => in.hsel && in.hreadyin || v }
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val grants = PriorityEncoderOH(requests)
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val s1_grants = Array.fill(n){Reg(init = Bool(true))}
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(s1_grants zip grants) foreach { case (g1, g) =>
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when (io.out.hready) { g1 := g }
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}
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def sel[T <: Data](in: Seq[T], s1: Seq[T]) =
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Vec((skb_valid zip s1 zip in) map { case ((v, s), in) => Mux(v, s, in) })
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io.out.haddr := Mux1H(grants, sel(io.ins.map(_.haddr), skb_haddr))
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io.out.hwrite := Mux1H(grants, sel(io.ins.map(_.hwrite), skb_hwrite))
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io.out.hsize := Mux1H(grants, sel(io.ins.map(_.hsize), skb_hsize))
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io.out.hburst := Mux1H(grants, sel(io.ins.map(_.hburst), skb_hburst))
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io.out.hprot := Mux1H(grants, sel(io.ins.map(_.hprot), skb_hprot))
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io.out.htrans := Mux1H(grants, sel(io.ins.map(_.htrans), skb_htrans))
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io.out.hmastlock := Mux1H(grants, sel(io.ins.map(_.hmastlock), skb_hmastlock))
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io.out.hsel := grants.reduce(_||_)
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(io.ins zipWithIndex) map { case (in, i) => {
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when (io.out.hready) {
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when (grants(i)) {
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skb_valid(i) := Bool(false)
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}
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when (!grants(i) && !skb_valid(i)) {
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val valid = in.hsel && in.hreadyin
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skb_valid(i) := valid
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when (valid) { // clock-gate
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skb_haddr(i) := in.haddr
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skb_hwrite(i) := in.hwrite
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skb_hsize(i) := in.hsize
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skb_hburst(i) := in.hburst
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skb_hprot(i) := in.hprot
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skb_htrans(i) := in.htrans
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skb_hmastlock(i) := in.hmastlock
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}
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}
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}
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} }
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io.out.hwdata := Mux1H(s1_grants, io.ins.map(_.hwdata))
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io.out.hreadyin := io.out.hready
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(io.ins zipWithIndex) foreach { case (in, i) => {
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val g1 = s1_grants(i)
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in.hrdata := dgate(g1, io.out.hrdata)
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in.hready := io.out.hready && (!skb_valid(i) || g1)
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in.hresp := dgate(g1, io.out.hresp)
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} }
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val amap = Seq({ (_:UInt) => Bool(true)})
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val bar = Module(new HastiXbar(n, amap))
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io.ins <> bar.io.masters
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io.out <> bar.io.slaves(0)
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}
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class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
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