Work around zero-width wire limitation in HTIF
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@ -150,12 +150,14 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
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val n = dataBits/short_request_bits
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val mem_req_data = (0 until n).map { i =>
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val ui = UInt(i, log2Up(n))
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def addr(offset: UInt) =
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if (dataBits == short_request_bits) offset
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else Cat(offset, UInt(i, log2Up(n)))
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when (state === state_mem_rresp && io.mem.grant.valid) {
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packet_ram(Cat(io.mem.grant.bits.addr_beat, ui)) :=
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packet_ram(addr(io.mem.grant.bits.addr_beat)) :=
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io.mem.grant.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
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}
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packet_ram(Cat(cnt, ui))
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packet_ram(addr(cnt))
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}.reverse.reduce(_##_)
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val init_addr = addr.toUInt >> (offsetBits-3)
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