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a9599302bd
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1c8745dfd2
@ -459,9 +459,12 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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// The mask and address during the address phase
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val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
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val a_mask = mask_shift(hastiDataBytes-1, 0)
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val a_mask = Wire(UInt(width = hastiDataBytes))
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val a_address = io.haddr >> UInt(hastiAlignment)
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val a_write = io.hwrite
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// for backwards compatibility with chisel2, we needed a static width in definition
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a_mask := mask_shift(hastiDataBytes-1, 0)
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// The data phase signals
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val d_read = RegEnable(a_request && !a_write, Bool(false), ready)
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