Remove most of mstatus when user mode isn't supported
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5442b89664
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00ea9a7d82
@ -363,7 +363,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_mstatus.prv := reg_mstatus.spp
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}.otherwise {
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when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
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when (reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
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.elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
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reg_mstatus.mpie := false
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reg_mstatus.mpp := PRV.U
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reg_mstatus.prv := reg_mstatus.mpp
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@ -388,7 +388,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_mstatus.mie := new_mstatus.mie
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reg_mstatus.mpie := new_mstatus.mpie
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val supportedModes = Vec((PRV.M :: PRV.U :: (if (usingVM) List(PRV.S) else Nil)).map(UInt(_)))
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val supportedModes = Vec((PRV.M +: (if (usingUser) Some(PRV.U) else None) ++: (if (usingVM) Seq(PRV.S) else Nil)).map(UInt(_)))
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if (supportedModes.size > 1) {
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reg_mstatus.mprv := new_mstatus.mprv
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when (supportedModes contains new_mstatus.mpp) { reg_mstatus.mpp := new_mstatus.mpp }
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@ -459,4 +459,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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io.rocc.csr.waddr := io.rw.addr
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io.rocc.csr.wdata := wdata
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io.rocc.csr.wen := wen
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if (!usingUser) {
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reg_mstatus.mpp := PRV.M
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reg_mstatus.prv := PRV.M
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reg_mstatus.mprv := false
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}
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}
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@ -14,6 +14,7 @@ case object XLen extends Field[Int]
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case object FetchWidth extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object UseUser extends Field[Boolean]
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case object UseAtomics extends Field[Boolean]
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case object UsePerfCounters extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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@ -32,6 +33,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
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val xLen = p(XLen)
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val usingVM = p(UseVM)
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val usingUser = p(UseUser)
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val usingFPU = p(UseFPU)
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val usingAtomics = p(UseAtomics)
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val usingFDivSqrt = p(FDivSqrt)
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