ahb: replace defective crossbar with a functional one
The previous crossbar had the following bugs:
1. a bursting master could be preempted
the AHB-lite spec requires a slave receive the entire burst
2. a waited master could be replaced
the AHB-lite spec requires haddr/etc to remain unchanged
3. hmastlock did no ensure exclusive access
atomic operations could be pre-empted
This commit is contained in:
Wesley W. Terpstra
@@ -96,6 +96,204 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
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val hresp = UInt(OUTPUT, SZ_HRESP)
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}
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/* A diverted master is told hready when his address phase goes nowhere.
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* In this case, we buffer his address phase request and replay it later.
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* NOTE: this must optimize to nothing when divert is constantly false.
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*/
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class MasterDiversion(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = (new HastiMasterIO).flip
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val out = (new HastiMasterIO)
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val divert = Bool(INPUT)
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}
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val full = Reg(init = Bool(false))
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val buffer = Reg(new HastiMasterIO)
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when (io.out.hready) {
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full := Bool(false)
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}
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when (io.divert) {
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full := Bool(true)
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buffer := io.in
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}
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// If the master is diverted, he must also have been told hready
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assert (!io.divert || io.in.hready);
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// Replay the request we diverted
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io.out.htrans := Mux(full, buffer.htrans, io.in.htrans)
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io.out.hmastlock := Mux(full, buffer.hmastlock, io.in.hmastlock)
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io.out.haddr := Mux(full, buffer.haddr, io.in.haddr)
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io.out.hwrite := Mux(full, buffer.hwrite, io.in.hwrite)
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io.out.hburst := Mux(full, buffer.hburst, io.in.hburst)
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io.out.hsize := Mux(full, buffer.hsize, io.in.hsize)
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io.out.hprot := Mux(full, buffer.hprot, io.in.hprot)
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io.out.hwdata := Mux(full, buffer.hwdata, io.in.hwdata)
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// Pass slave response back
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io.in.hrdata := io.out.hrdata
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io.in.hresp := io.out.hresp
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io.in.hready := io.out.hready && !full // Block master while we steal his address phase
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}
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/* Masters with lower index have priority over higher index masters.
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* However, a lower priority master will retain control of a slave when EITHER:
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* 1. a burst is in progress (switching slaves mid-burst violates AHB-lite at slave)
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* 2. a transfer was waited (the standard forbids changing requests in this case)
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*
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* If a master raises hmastlock, it will be waited until no other master has inflight
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* requests; then, it acquires exclusive control of the crossbar until hmastlock is low.
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*
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* To implement an AHB-lite crossbar, it is important to realize that requests and
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* responses are coupled. Unlike modern bus protocols where the response data has flow
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* control independent of the request data, in AHB-lite, both flow at the same time at
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* the sole discretion of the slave via the hready signal. The address and data are
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* delivered on two back-to-back cycles, the so-called address and data phases.
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*
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* Masters can only be connected to a single slave at a time. If a master had two different
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* slave connections on the address and data phases, there would be two independent hready
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* signals. An AHB-lite slave can assume that data flows when it asserts hready. If the data
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* slave deasserts hready while the address slave asserts hready, the master is put in the
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* impossible position of being in data phase on two slaves at once. For this reason, when
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* a master issues back-to-back accesses to distinct slaves, we inject a pipeline bubble
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* between the two requests to limit the master to just a single slave at a time.
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*
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* Conversely, a slave CAN have two masters attached to it. This is unproblematic, because
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* the only signal which governs data flow is hready. Thus, both masters can be stalled
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* safely by the single slave.
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*/
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class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val masters = Vec(nMasters, new HastiMasterIO).flip
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val slaves = Vec(addressMap.size, new HastiSlaveIO).flip
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}
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val nSlaves = addressMap.size
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// !!! handle hmastlock
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// Setup diversions infront of each master
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val diversions = Seq.tabulate(nMasters) { m => Module(new MasterDiversion) }
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(io.masters zip diversions) foreach { case (m, d) => d.io.in <> m }
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// Handy short-hand
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val masters = diversions map (_.io.out)
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val slaves = io.slaves
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// This matrix governs the master-slave connections in the address phase
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// It is indexed by addressPhaseGrantSM(slave)(master)
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// It is guaranteed to have at most one 'true' per column and per row
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val addressPhaseGrantSM = Wire(Vec(nSlaves, Vec(nMasters, Bool())))
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// This matrix governs the master-slave connections in the data phase
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// It is guaranteed to have at most one 'true' per column and per row
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val dataPhaseGrantSM = Reg (init = Vec.fill(nSlaves)(Vec.fill(nMasters)(Bool(false))))
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// This matrix is the union of the address and data phases.
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// It is transposed with respect to the two previous matrices.
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// It is guaranteed to contain at most one 'true' per master row.
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// However, two 'true's per slave column are permitted.
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val unionGrantMS = Vec.tabulate(nMasters) { m => Vec.tabulate(nSlaves) { s =>
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addressPhaseGrantSM(s)(m) || dataPhaseGrantSM(s)(m) } }
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// Confirm the guarantees made above
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def justOnce(v: Vec[Bool]) = v.fold(Bool(false)) { case (p, v) =>
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assert (!p || !v)
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p || v
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}
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addressPhaseGrantSM foreach { s => justOnce(s) }
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unionGrantMS foreach { s => justOnce(s) }
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// Data phase follows address phase whenever the slave is ready
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(slaves zip (dataPhaseGrantSM zip addressPhaseGrantSM)) foreach { case (s, (d, a)) =>
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when (s.hready) { d := a }
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}
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// Record the grant state from the previous cycle; needed in case we hold access
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val priorAddressPhaseGrantSM = RegNext(addressPhaseGrantSM)
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// If a master says BUSY or SEQ, it is in the middle of a burst.
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// In this case, it MUST stay attached to the same slave as before.
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// Otherwise, it would violate the AHB-lite specification as seen by
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// the slave, which is guaranteed a complete burst of the promised length.
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// One case where this matters is preventing preemption of low-prio masters.
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// NOTE: this exposes a slave to bad addresses when a master is buggy
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val holdBurstM = Vec(masters map { _.isHold() })
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// Transform the burst hold requirement from master indexing to slave indexing
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// We use the previous cycle's binding because the master continues the prior burst
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val holdBurstS = Vec(priorAddressPhaseGrantSM map { m => Mux1H(m, holdBurstM) })
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// If a slave says !hready to a request, it must retain the same master next cycle.
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// The AHB-lite specification requires that a waited transfer remain unchanged.
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// If we preempted a waited master, the new master's request could potentially differ.
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val holdBusyS = RegNext(Vec(slaves map { s => !s.hready && s.hsel }))
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// Combine the above two grounds to determine if the slave retains its prior master
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val holdS = Vec((holdBurstS zip holdBusyS) map ({ case (a,b) => a||b }))
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// Determine which master addresses match which slaves
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val matchMS = Vec(masters map { m => Vec(addressMap map { afn => afn(m.haddr) }) })
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// Detect requests to nowhere; we need to allow progress in this case
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val nowhereM = Vec(matchMS map { s => !s.reduce(_ || _) })
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// Detect if we need to inject a pipeline bubble between the master requests.
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// Divert masters already granted a data phase different from next request.
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// NOTE: if only one slave, matchMS is always true => bubble always false
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// => the diversion registers are optimized away as they are unread
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// NOTE: bubble => dataPhase => have an hready signal
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val bubbleM =
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Vec.tabulate(nMasters) { m =>
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Vec.tabulate(nSlaves) { s => dataPhaseGrantSM(s)(m) && !matchMS(m)(s) }
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.reduce(_ || _) }
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// Requested access to slaves from masters (pre-arbitration)
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// NOTE: isNSeq does NOT include SEQ; thus, masters who are midburst do not
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// request access to a new slave. They stay tied to the old and do not get two.
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// NOTE: if a master was waited, it must repeat the same request as last cycle;
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// thus, it will request the same slave and not end up with two (unless buggy).
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val NSeq = Vec(masters.map(_.isNSeq()))
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val requestSM = Vec.tabulate(nSlaves) { s => Vec.tabulate(nMasters) { m => matchMS(m)(s) && NSeq(m) && !bubbleM(m) } }
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// Select at most one master request per slave (lowest index = highest priority)
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val selectedRequestSM = Vec(requestSM map { m => Vec(PriorityEncoderOH(m)) })
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// Calculate new crossbar interconnect state
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addressPhaseGrantSM := Vec((holdS zip (priorAddressPhaseGrantSM zip selectedRequestSM))
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map { case (h, (p, r)) => Mux(h, p, r) })
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// If we diverted a master, we need to absorb his address phase to replay later
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for (m <- 0 until nMasters) {
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diversions(m).io.divert := bubbleM(m) && NSeq(m) && masters(m).hready
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}
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// Master muxes (address and data phase are the same)
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(masters zip (unionGrantMS zip nowhereM)) foreach { case (m, (g, n)) => {
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// If the master is connected to a slave, the slave determines hready.
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// However, if no slave is connected, for progress report ready anyway, if:
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// bad address (swallow request) OR idle (permit stupid slaves to move FSM)
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val autoready = n || m.isIdle()
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m.hready := Mux1H(g, slaves.map(_.hready ^ autoready)) ^ autoready
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m.hrdata := Mux1H(g, slaves.map(_.hrdata))
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m.hresp := Mux1H(g, slaves.map(_.hresp))
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} }
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// Slave address phase muxes
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(slaves zip addressPhaseGrantSM) foreach { case (s, g) => {
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s.htrans := Mux1H(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0)
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s.haddr := Mux1H(g, masters.map(_.haddr))
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s.hmastlock := Mux1H(g, masters.map(_.hmastlock)) // !!! use global crossbar lock state
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s.hwrite := Mux1H(g, masters.map(_.hwrite))
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s.hsize := Mux1H(g, masters.map(_.hsize))
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s.hburst := Mux1H(g, masters.map(_.hburst))
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s.hprot := Mux1H(g, masters.map(_.hprot))
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s.hsel := g.reduce(_ || _)
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} }
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// Slave data phase muxes
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(slaves zip dataPhaseGrantSM) foreach { case (s, g) => {
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s.hwdata := Mux1H(g, masters.map(_.hwdata))
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} }
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}
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class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val master = new HastiMasterIO().flip
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@@ -236,23 +434,6 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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} }
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}
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class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])
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(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val masters = Vec(nMasters, new HastiMasterIO).flip
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val slaves = Vec(addressMap.size, new HastiSlaveIO).flip
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}
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val buses = List.fill(nMasters){Module(new HastiBus(addressMap))}
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val muxes = List.fill(addressMap.size){Module(new HastiSlaveMux(nMasters))}
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(buses.map(b => b.io.master) zip io.masters) foreach { case (b, m) => b <> m }
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(muxes.map(m => m.io.out) zip io.slaves ) foreach { case (x, s) => x <> s }
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for (m <- 0 until nMasters; s <- 0 until addressMap.size) yield {
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buses(m).io.slaves(s) <> muxes(s).io.ins(m)
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}
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}
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class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = new HastiSlaveIO
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