ahb: rename hreadyout to standard hready, mark hreadyin for death
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@ -86,10 +86,10 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
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val hwdata = Bits(INPUT, hastiDataBits)
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val hrdata = Bits(OUTPUT, hastiDataBits)
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val hsel = Bool(INPUT)
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val hreadyin = Bool(INPUT)
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val hreadyout = Bool(OUTPUT)
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val hresp = UInt(OUTPUT, SZ_HRESP)
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val hsel = Bool(INPUT)
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val hreadyin = Bool(INPUT) // !!! non-standard signal
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val hready = Bool(OUTPUT)
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val hresp = UInt(OUTPUT, SZ_HRESP)
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}
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class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModule()(p) {
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@ -137,11 +137,11 @@ class HastiBus(amap: Seq[UInt=>Bool])(implicit p: Parameters) extends HastiModul
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} }
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val s1_hsels = Array.fill(amap.size){Reg(init = Bool(false))}
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val hreadyouts = io.slaves.map(_.hreadyout)
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val master_hready = s1_hsels.reduce(_||_) === Bool(false) || Mux1H(s1_hsels, hreadyouts)
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val hreadys = io.slaves.map(_.hready)
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val master_hready = s1_hsels.reduce(_||_) === Bool(false) || Mux1H(s1_hsels, hreadys)
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when (master_hready) {
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val skid = s1_hsels.reduce(_||_) && (hsels zip hreadyouts).map{ case (s, r) => s && !r }.reduce(_||_)
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val skid = s1_hsels.reduce(_||_) && (hsels zip hreadys).map{ case (s, r) => s && !r }.reduce(_||_)
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skb_valid := skid
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when (skid) {
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skb_haddr := io.master.haddr
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@ -185,7 +185,7 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val s1_grants = Array.fill(n){Reg(init = Bool(true))}
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(s1_grants zip grants) foreach { case (g1, g) =>
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when (io.out.hreadyout) { g1 := g }
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when (io.out.hready) { g1 := g }
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}
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def sel[T <: Data](in: Seq[T], s1: Seq[T]) =
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@ -201,7 +201,7 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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io.out.hsel := grants.reduce(_||_)
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(io.ins zipWithIndex) map { case (in, i) => {
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when (io.out.hreadyout) {
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when (io.out.hready) {
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when (grants(i)) {
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skb_valid(i) := Bool(false)
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}
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@ -222,12 +222,12 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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} }
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io.out.hwdata := Mux1H(s1_grants, io.ins.map(_.hwdata))
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io.out.hreadyin := io.out.hreadyout
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io.out.hreadyin := io.out.hready
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(io.ins zipWithIndex) foreach { case (in, i) => {
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val g1 = s1_grants(i)
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in.hrdata := dgate(g1, io.out.hrdata)
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in.hreadyout := io.out.hreadyout && (!skb_valid(i) || g1)
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in.hready := io.out.hready && (!skb_valid(i) || g1)
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in.hresp := dgate(g1, io.out.hresp)
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} }
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}
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@ -264,7 +264,7 @@ class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
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io.out.hmastlock := io.in.hmastlock
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io.out.hwdata := io.in.hwdata
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io.in.hrdata := io.out.hrdata
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io.in.hreadyout := io.out.hready
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io.in.hready := io.out.hready
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io.in.hresp := io.out.hresp
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}
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@ -52,7 +52,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
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io.out.penable := (state === s_access)
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io.out.pwdata := io.in.hwdata
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io.in.hrdata := io.out.prdata
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io.in.hreadyout := ((state === s_access) & io.out.pready) | (state === s_idle)
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io.in.hready := ((state === s_access) & io.out.pready) | (state === s_idle)
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io.in.hresp := io.out.pslverr
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}
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