Don't rely on Mux1H output when no inputs are hot
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@ -272,20 +272,23 @@ class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Paramete
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diversions(m).io.divert := bubbleM(m) && NSeq(m) && masters(m).hready
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}
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def dotProduct(g: Seq[Bool], v: Seq[UInt]) =
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(g zip v) map { case (gg, ss) => Mux(gg, ss, ss.fromBits(UInt(0))) } reduce (_|_)
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// Master muxes (address and data phase are the same)
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(masters zip (unionGrantMS zip nowhereM)) foreach { case (m, (g, n)) => {
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// If the master is connected to a slave, the slave determines hready.
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// However, if no slave is connected, for progress report ready anyway, if:
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// bad address (swallow request) OR idle (permit stupid slaves to move FSM)
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val autoready = n || m.isIdle()
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m.hready := Mux1H(g, slaves.map(_.hready ^ autoready)) ^ autoready
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m.hready := dotProduct(g, slaves.map(_.hready ^ autoready)) ^ autoready
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m.hrdata := Mux1H(g, slaves.map(_.hrdata))
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m.hresp := Mux1H(g, slaves.map(_.hresp))
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} }
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// Slave address phase muxes
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(slaves zip addressPhaseGrantSM) foreach { case (s, g) => {
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s.htrans := Mux1H(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0)
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s.htrans := dotProduct(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0)
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s.haddr := Mux1H(g, masters.map(_.haddr))
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s.hmastlock := isLocked
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s.hwrite := Mux1H(g, masters.map(_.hwrite))
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