By default, use same TileLink width everywhere
When there's no L2 with a wide interface, having wider TileLink is only disadvantageous.
This commit is contained in:
2
chisel3
2
chisel3
Submodule chisel3 updated: d742d70a05...3b10267257
Submodule groundtest updated: 49b713c4fb...f44383cd9b
Submodule junctions updated: f1c609d74a...9522bc5a2a
2
rocket
2
rocket
Submodule rocket updated: 05b951ba6f...a2c51cfabe
@ -260,6 +260,7 @@ class BaseConfig extends Config (
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = site(MIFDataBeats),
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("L2toMC") =>
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TileLinkParameters(
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@ -271,6 +272,7 @@ class BaseConfig extends Config (
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBeats = site(MIFDataBeats),
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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@ -287,6 +289,7 @@ class BaseConfig extends Config (
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBeats = site(MIFDataBeats),
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dataBits = site(CacheBlockBytes) * 8)
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}
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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@ -23,6 +23,7 @@ class WithGroundTest extends Config(
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = site(MIFDataBeats),
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dataBits = site(CacheBlockBytes)*8)
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case BuildTiles => {
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val groundtest = if (site(XLen) == 64)
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@ -42,6 +43,7 @@ class WithGroundTest extends Config(
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case TohostAddr => BigInt("80001000", 16)
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case RoccNCSRs => site(GroundTestCSRs).size
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case UseFPU => false
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case UseAtomics => true
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case _ => throw new CDEMatchError
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})
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2
uncore
2
uncore
Submodule uncore updated: 1bb32abf97...e37eea2c33
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