By default, use same TileLink width everywhere

When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.

chisel3

@@ -1 +1 @@
-Subproject commit d742d70a05b5fa997517ea7b5eb2d15b23e7a431
+Subproject commit 3b10267257de7662abbbc235d9bfd8a8b89f69f5

groundtest

@@ -1 +1 @@
-Subproject commit 49b713c4fbb6660b6d86a7e19ea048d6d7aeb17a
+Subproject commit f44383cd9b12cc1f58a5e4a278e3e3b65d34346d

junctions

@@ -1 +1 @@
-Subproject commit f1c609d74af26bf1df4bfcc90c9db4c7c08224ff
+Subproject commit 9522bc5a2a3e45601a0578f3f7ff1a84979cdf02

rocket

@@ -1 +1 @@
-Subproject commit 05b951ba6f9cce36b0a3b29af9be7bd643ba2b66
+Subproject commit a2c51cfabe3029121b5f8d8136a8137da5e2802f

src/main/scala/Configs.scala

@@ -260,6 +260,7 @@ class BaseConfig extends Config (
               if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
           maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
           maxManagerXacts = site(NAcquireTransactors) + 2,
+          dataBeats = site(MIFDataBeats),
           dataBits = site(CacheBlockBytes)*8)
       case TLKey("L2toMC") => 
         TileLinkParameters(
@@ -271,6 +272,7 @@ class BaseConfig extends Config (
           maxClientXacts = 1,
           maxClientsPerPort = site(NAcquireTransactors) + 2,
           maxManagerXacts = 1,
+          dataBeats = site(MIFDataBeats),
           dataBits = site(CacheBlockBytes)*8)
       case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
         maxClientXacts = site(NAcquireTransactors) + 2,
@@ -287,6 +289,7 @@ class BaseConfig extends Config (
           maxClientXacts = 4,
           maxClientsPerPort = 1,
           maxManagerXacts = 1,
+          dataBeats = site(MIFDataBeats),
           dataBits = site(CacheBlockBytes) * 8)
       }
       case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))

src/main/scala/TestConfigs.scala

@@ -23,6 +23,7 @@ class WithGroundTest extends Config(
           if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
         maxClientsPerPort = 2,
         maxManagerXacts = site(NAcquireTransactors) + 2,
+        dataBeats = site(MIFDataBeats),
         dataBits = site(CacheBlockBytes)*8)
     case BuildTiles => {
       val groundtest = if (site(XLen) == 64)
@@ -42,6 +43,7 @@ class WithGroundTest extends Config(
     case TohostAddr => BigInt("80001000", 16)
     case RoccNCSRs => site(GroundTestCSRs).size
     case UseFPU => false
+    case UseAtomics => true
     case _ => throw new CDEMatchError
   })
 

uncore

@@ -1 +1 @@
-Subproject commit 1bb32abf97b256be31f8876579e27c2fd9f5a958
+Subproject commit e37eea2c33c510c18d1b7f750f45a92dcadb91b1