ahb: put signals in the order they appear in signal traces in the spec
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@ -59,16 +59,16 @@ abstract class HastiBundle(implicit val p: Parameters) extends ParameterizedBund
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with HasHastiParameters
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class HastiMasterIO(implicit p: Parameters) extends HastiBundle()(p) {
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val haddr = UInt(OUTPUT, hastiAddrBits)
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val hwrite = Bool(OUTPUT)
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val hsize = UInt(OUTPUT, SZ_HSIZE)
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val hburst = UInt(OUTPUT, SZ_HBURST)
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val hprot = UInt(OUTPUT, SZ_HPROT)
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val htrans = UInt(OUTPUT, SZ_HTRANS)
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val hmastlock = Bool(OUTPUT)
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val haddr = UInt(OUTPUT, hastiAddrBits)
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val hwrite = Bool(OUTPUT)
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val hburst = UInt(OUTPUT, SZ_HBURST)
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val hsize = UInt(OUTPUT, SZ_HSIZE)
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val hprot = UInt(OUTPUT, SZ_HPROT)
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val hwdata = Bits(OUTPUT, hastiDataBits)
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val hrdata = Bits(INPUT, hastiDataBits)
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val hrdata = Bits(INPUT, hastiDataBits)
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val hready = Bool(INPUT)
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val hresp = UInt(INPUT, SZ_HRESP)
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@ -79,15 +79,15 @@ class HastiMasterIO(implicit p: Parameters) extends HastiBundle()(p) {
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}
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class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
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val haddr = UInt(INPUT, hastiAddrBits)
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val hwrite = Bool(INPUT)
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val hsize = UInt(INPUT, SZ_HSIZE)
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val hburst = UInt(INPUT, SZ_HBURST)
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val hprot = UInt(INPUT, SZ_HPROT)
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val htrans = UInt(INPUT, SZ_HTRANS)
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val hmastlock = Bool(INPUT)
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val haddr = UInt(INPUT, hastiAddrBits)
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val hwrite = Bool(INPUT)
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val hburst = UInt(INPUT, SZ_HBURST)
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val hsize = UInt(INPUT, SZ_HSIZE)
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val hprot = UInt(INPUT, SZ_HPROT)
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val hwdata = Bits(INPUT, hastiDataBits)
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val hwdata = Bits(INPUT, hastiDataBits)
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val hrdata = Bits(OUTPUT, hastiDataBits)
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val hsel = Bool(INPUT)
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@ -319,21 +319,21 @@ class HastiSlaveMux(n: Int)(implicit p: Parameters) extends HastiModule()(p) {
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class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
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val io = new Bundle {
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val in = new HastiSlaveIO
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val in = new HastiSlaveIO
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val out = new HastiMasterIO
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}
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io.out.haddr := io.in.haddr
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io.out.hwrite := io.in.hwrite
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io.out.hsize := io.in.hsize
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io.out.hburst := io.in.hburst
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io.out.hprot := io.in.hprot
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io.out.htrans := Mux(io.in.hsel && io.in.hreadyin, io.in.htrans, HTRANS_IDLE)
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io.out.htrans := Mux(io.in.hsel && io.in.hreadyin, io.in.htrans, HTRANS_IDLE)
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io.out.hmastlock := io.in.hmastlock
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io.out.hwdata := io.in.hwdata
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io.out.haddr := io.in.haddr
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io.out.hwrite := io.in.hwrite
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io.out.hburst := io.in.hburst
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io.out.hsize := io.in.hsize
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io.out.hprot := io.in.hprot
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io.out.hwdata := io.in.hwdata
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io.in.hrdata := io.out.hrdata
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io.in.hready := io.out.hready
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io.in.hresp := io.out.hresp
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io.in.hresp := io.out.hresp
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}
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class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule()(p)
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