riscv/rocket-chip
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Fix TLB tag check logic when ASIDs are present

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This commit is contained in:
Andrew Waterman 2016-05-27 12:24:17 -07:00
parent c104b57c52
commit 3ee5144923
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/tlb.scala
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@ -92,7 +92,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val r_refill_waddr = Reg(tag_cam.io.write_addr)
val r_req = Reg(new TLBReq)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid
tag_cam.io.write_tag := r_refill_tag