Avoid floating-point arithmetic where integers suffice
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@ -432,8 +432,8 @@ class DebugModule ()(implicit val p:cde.Parameters)
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val sbRamAddrWidth = log2Up((cfg.nDebugRamBytes * 8) / sbRamDataWidth)
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val sbRamAddrOffset = log2Up(tlDataBits/8)
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val ramDataWidth = max(dbRamDataWidth, sbRamDataWidth)
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val ramAddrWidth = min(dbRamAddrWidth, sbRamAddrWidth)
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val ramDataWidth = dbRamDataWidth max sbRamDataWidth
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val ramAddrWidth = dbRamAddrWidth min sbRamAddrWidth
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val ramMem = Mem(1 << ramAddrWidth , UInt(width=ramDataWidth))
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val ramAddr = Wire(UInt(width=ramAddrWidth))
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val ramRdData = Wire(UInt(width=ramDataWidth))
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@ -47,7 +47,7 @@ class ParityCode extends Code
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class SECCode extends Code
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{
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def width(k: Int) = {
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val m = new Unsigned(k).log2 + 1
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val m = log2Floor(k) + 1
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k + m + (if((1 << m) < m+k+1) 1 else 0)
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}
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def encode(x: UInt) = {
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@ -3,15 +3,6 @@
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package uncore
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import Chisel._
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import scala.math._
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class Unsigned(x: Int) {
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require(x >= 0)
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def clog2: Int = { require(x > 0); ceil(log(x)/log(2)).toInt }
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def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt }
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def isPow2: Boolean = x > 0 && (x & (x-1)) == 0
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def nextPow2: Int = if (x == 0) 1 else 1 << clog2
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}
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object MuxBundle {
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def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
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