another fix for AXI -> AHB converter
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@ -384,7 +384,7 @@ class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule(
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val is_rtrans = (state === s_read) &&
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(io.hasti.htrans === HTRANS_SEQ ||
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io.hasti.htrans === HTRANS_NONSEQ)
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val rvalid = Reg(next = is_rtrans)
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val rvalid = Reg(is_rtrans, io.hasti.hready)
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io.nasti.aw.ready := (state === s_idle)
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io.nasti.ar.ready := (state === s_idle) && !io.nasti.aw.valid
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