Use Mem for ReorderQueue data
This might improve FPGA QoR.
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@ -182,7 +182,7 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
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val deq = new ReorderDequeueIO(dType, tagWidth)
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}
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val roq_data = Reg(Vec(size, dType.cloneType))
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val roq_data = Mem(size, dType.cloneType)
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val roq_tags = Reg(Vec(size, UInt(width = tagWidth)))
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val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
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