Fix BRAM assertion condition
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@ -38,7 +38,7 @@ class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
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val rdata = bram.read(raddr, ren)
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val wdata = io.acquire.bits.data
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val wmask = io.acquire.bits.wmask()
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assert(!io.acquire.valid || wmask === Fill(tlDataBytes, Bool(true)),
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assert(!wen || (wmask === Fill(tlDataBytes, Bool(true))),
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"bram: subblock writes not supported")
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when (wen) {
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bram.write(s0_addr, wdata)
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