Use buses, rather than crossbars, by default in TLInterconnect
We should eventually parameterize this, of course.
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@ -110,11 +110,11 @@ class PortedTileLinkCrossbar(
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val phyHdrWidth = log2Up(n)
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val count = tlDataBeats
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
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val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
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val prbNet = Module(new BasicCrossbar(n, new Probe))
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val gntNet = Module(new BasicCrossbar(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData())))
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val ackNet = Module(new BasicCrossbar(n, new Finish))
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val acqNet = Module(new BasicBus(CrossbarConfig(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))))
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val relNet = Module(new BasicBus(CrossbarConfig(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))))
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val prbNet = Module(new BasicBus(CrossbarConfig(n, new Probe)))
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val gntNet = Module(new BasicBus(CrossbarConfig(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData()))))
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val ackNet = Module(new BasicBus(CrossbarConfig(n, new Finish)))
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// Aliases for the various network IO bundle types
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type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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@ -19,19 +19,34 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
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}
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class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
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val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip
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val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType)))
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val in = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip
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val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType)))
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}
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abstract class PhysicalNetwork extends Module
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class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork {
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val io = new BasicCrossbarIO(n, dType)
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case class CrossbarConfig[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None)
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abstract class AbstractCrossbar[T <: Data](conf: CrossbarConfig[T]) extends PhysicalNetwork {
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val io = new BasicCrossbarIO(conf.n, conf.dType)
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}
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class BasicBus[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
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val arb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
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arb.io.in <> io.in
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arb.io.out.ready := io.out(arb.io.out.bits.header.dst).ready
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for ((out, i) <- io.out zipWithIndex) {
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out.valid := arb.io.out.valid && arb.io.out.bits.header.dst === UInt(i)
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out.bits := arb.io.out.bits
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}
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}
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class BasicCrossbar[T <: Data](conf: CrossbarConfig[T]) extends AbstractCrossbar(conf) {
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io.in.foreach { _.ready := Bool(false) }
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io.out.zipWithIndex.map{ case (out, i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock))
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.n, conf.count, conf.needsLock))
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(rrarb.io.in, io.in).zipped.map{ case (arb, in) => {
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val destined = in.bits.header.dst === UInt(i)
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arb.valid := in.valid && destined
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